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| author | Tristan Gingold <tgingold@free.fr> | 2019-08-16 11:09:29 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-08-16 11:09:29 +0200 |
| commit | 589b4a049acf4ad51886750b209c6a8073fb94e7 (patch) | |
| tree | ecfc082f61cb38f59876453d18768c8e0b3eb39f /python/libghdl/thin/vhdl/nodes.py | |
| parent | a523865a36f56882d1d0653ba9b98c65138627f5 (diff) | |
| download | ghdl-589b4a049acf4ad51886750b209c6a8073fb94e7.tar.gz ghdl-589b4a049acf4ad51886750b209c6a8073fb94e7.tar.bz2 ghdl-589b4a049acf4ad51886750b209c6a8073fb94e7.zip | |
vhdl: recognize PSL units reserved words.
Diffstat (limited to 'python/libghdl/thin/vhdl/nodes.py')
| -rw-r--r-- | python/libghdl/thin/vhdl/nodes.py | 68 |
1 files changed, 41 insertions, 27 deletions
diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index 5983c4972..3e2ff1972 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -1108,33 +1108,47 @@ class Iir_Predefined: Ieee_Numeric_Std_Ne_Sgn_Sgn = 241 Ieee_Numeric_Std_Ne_Sgn_Int = 242 Ieee_Numeric_Std_Ne_Int_Sgn = 243 - Ieee_Numeric_Std_Neg_Uns = 244 - Ieee_Numeric_Std_Neg_Sgn = 245 - Ieee_Math_Real_Ceil = 246 - Ieee_Math_Real_Log2 = 247 - Ieee_Std_Logic_Unsigned_Add_Slv_Slv = 248 - Ieee_Std_Logic_Unsigned_Add_Slv_Int = 249 - Ieee_Std_Logic_Unsigned_Add_Int_Slv = 250 - Ieee_Std_Logic_Unsigned_Add_Slv_Sl = 251 - Ieee_Std_Logic_Unsigned_Add_Sl_Slv = 252 - Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 253 - Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 254 - Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 255 - Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 256 - Ieee_Std_Logic_Unsigned_Le_Slv_Int = 257 - Ieee_Std_Logic_Unsigned_Le_Int_Slv = 258 - Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 259 - Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 260 - Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 261 - Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 262 - Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 263 - Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 264 - Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 265 - Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 266 - Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 267 - Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 268 - Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 269 - Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 270 + Ieee_Numeric_Std_Not_Uns = 244 + Ieee_Numeric_Std_Not_Sgn = 245 + Ieee_Numeric_Std_And_Uns_Uns = 246 + Ieee_Numeric_Std_And_Sgn_Sgn = 247 + Ieee_Numeric_Std_Or_Uns_Uns = 248 + Ieee_Numeric_Std_Or_Sgn_Sgn = 249 + Ieee_Numeric_Std_Nand_Uns_Uns = 250 + Ieee_Numeric_Std_Nand_Sgn_Sgn = 251 + Ieee_Numeric_Std_Nor_Uns_Uns = 252 + Ieee_Numeric_Std_Nor_Sgn_Sgn = 253 + Ieee_Numeric_Std_Xor_Uns_Uns = 254 + Ieee_Numeric_Std_Xor_Sgn_Sgn = 255 + Ieee_Numeric_Std_Xnor_Uns_Uns = 256 + Ieee_Numeric_Std_Xnor_Sgn_Sgn = 257 + Ieee_Numeric_Std_Neg_Uns = 258 + Ieee_Numeric_Std_Neg_Sgn = 259 + Ieee_Math_Real_Ceil = 260 + Ieee_Math_Real_Log2 = 261 + Ieee_Std_Logic_Unsigned_Add_Slv_Slv = 262 + Ieee_Std_Logic_Unsigned_Add_Slv_Int = 263 + Ieee_Std_Logic_Unsigned_Add_Int_Slv = 264 + Ieee_Std_Logic_Unsigned_Add_Slv_Sl = 265 + Ieee_Std_Logic_Unsigned_Add_Sl_Slv = 266 + Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 267 + Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 268 + Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 269 + Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 270 + Ieee_Std_Logic_Unsigned_Le_Slv_Int = 271 + Ieee_Std_Logic_Unsigned_Le_Int_Slv = 272 + Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 273 + Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 274 + Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 275 + Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 276 + Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 277 + Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 278 + Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 279 + Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 280 + Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 281 + Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 282 + Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 283 + Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 284 Get_Kind = libghdl.vhdl__nodes__get_kind Get_Location = libghdl.vhdl__nodes__get_location |