Reworked symbols.

3 files changed, 35 insertions, 39 deletions

diff --git a/pyGHDL/dom/Aggregates.py b/pyGHDL/dom/Aggregates.py
index 32dc1cacf..8edd037a1 100644
--- a/pyGHDL/dom/Aggregates.py
+++ b/pyGHDL/dom/Aggregates.py
@@ -48,12 +48,11 @@ from pyVHDLModel.VHDLModel import (
     NamedAggregateElement as VHDLModel_NamedAggregateElement,
     OthersAggregateElement as VHDLModel_OthersAggregateElement,
     Expression,
+    Symbol,
 )
 from pyGHDL.libghdl._types import Iir
 from pyGHDL.dom import DOMMixin
 from pyGHDL.dom.Range import Range
-from pyGHDL.dom.Symbol import EnumerationLiteralSymbol
-
 
 __all__ = []
 
@@ -61,43 +60,30 @@ __all__ = []
 @export
 class SimpleAggregateElement(VHDLModel_SimpleAggregateElement, DOMMixin):
     def __init__(self, node: Iir, expression: Expression):
-        super().__init__()
+        super().__init__(expression)
         DOMMixin.__init__(self, node)
 
-        self._expression = expression
-
 
 @export
 class IndexedAggregateElement(VHDLModel_IndexedAggregateElement, DOMMixin):
     def __init__(self, node: Iir, index: Expression, expression: Expression):
-        super().__init__()
+        super().__init__(index, expression)
         DOMMixin.__init__(self, node)
 
-        self._index = index
-        self._expression = expression
-
 
 @export
 class RangedAggregateElement(VHDLModel_RangedAggregateElement, DOMMixin):
-    def __init__(self, node: Iir, r: Range, expression: Expression):
-        super().__init__()
+    def __init__(self, node: Iir, rng: Range, expression: Expression):
+        super().__init__(rng, expression)
         DOMMixin.__init__(self, node)
 
-        self._range = r
-        self._expression = expression
-
 
 @export
 class NamedAggregateElement(VHDLModel_NamedAggregateElement, DOMMixin):
-    def __init__(
-        self, node: Iir, name: EnumerationLiteralSymbol, expression: Expression
-    ):
-        super().__init__()
+    def __init__(self, node: Iir, name: Symbol, expression: Expression):
+        super().__init__(name, expression)
         DOMMixin.__init__(self, node)
 
-        self._name = name
-        self._expression = expression
-
 
 @export
 class OthersAggregateElement(VHDLModel_OthersAggregateElement, DOMMixin):
diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py
index 2dd82ed97..3dc1271f2 100644
--- a/pyGHDL/dom/Expression.py
+++ b/pyGHDL/dom/Expression.py
@@ -77,13 +77,14 @@ from pyVHDLModel.VHDLModel import (
     Expression,
     AggregateElement,
     SubTypeOrSymbol,
+    Symbol,
 )
 
 from pyGHDL.libghdl import utils
 from pyGHDL.libghdl._types import Iir
 from pyGHDL.libghdl.vhdl import nodes
 from pyGHDL.dom._Utils import GetIirKindOfNode
-from pyGHDL.dom.Symbol import EnumerationLiteralSymbol, SimpleSubTypeSymbol
+from pyGHDL.dom.Symbol import SimpleSubTypeSymbol
 from pyGHDL.dom.Aggregates import (
     OthersAggregateElement,
     SimpleAggregateElement,
@@ -116,28 +117,36 @@ class _ParseBinaryExpressionMixin:
 
 
 @export
-class InverseExpression(VHDLModel_InverseExpression, DOMMixin, _ParseUnaryExpressionMixin):
+class InverseExpression(
+    VHDLModel_InverseExpression, DOMMixin, _ParseUnaryExpressionMixin
+):
     def __init__(self, node: Iir, operand: Expression):
         super().__init__(operand)
         DOMMixin.__init__(self, node)
 
 
 @export
-class IdentityExpression(VHDLModel_IdentityExpression, DOMMixin, _ParseUnaryExpressionMixin):
+class IdentityExpression(
+    VHDLModel_IdentityExpression, DOMMixin, _ParseUnaryExpressionMixin
+):
     def __init__(self, node: Iir, operand: Expression):
         super().__init__(operand)
         DOMMixin.__init__(self, node)
 
 
 @export
-class NegationExpression(VHDLModel_NegationExpression, DOMMixin, _ParseUnaryExpressionMixin):
+class NegationExpression(
+    VHDLModel_NegationExpression, DOMMixin, _ParseUnaryExpressionMixin
+):
     def __init__(self, node: Iir, operand: Expression):
         super().__init__(operand)
         DOMMixin.__init__(self, node)
 
 
 @export
-class AbsoluteExpression(VHDLModel_AbsoluteExpression, DOMMixin, _ParseUnaryExpressionMixin):
+class AbsoluteExpression(
+    VHDLModel_AbsoluteExpression, DOMMixin, _ParseUnaryExpressionMixin
+):
     def __init__(self, node: Iir, operand: Expression):
         super().__init__(operand)
         DOMMixin.__init__(self, node)
@@ -257,7 +266,9 @@ class RemainderExpression(
 
 
 @export
-class ModuloExpression(VHDLModel_ModuloExpression, DOMMixin, _ParseBinaryExpressionMixin):
+class ModuloExpression(
+    VHDLModel_ModuloExpression, DOMMixin, _ParseBinaryExpressionMixin
+):
     def __init__(self, node: Iir, left: Expression, right: Expression):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
@@ -322,7 +333,9 @@ class EqualExpression(VHDLModel_EqualExpression, DOMMixin, _ParseBinaryExpressio
 
 
 @export
-class UnequalExpression(VHDLModel_UnequalExpression, DOMMixin, _ParseBinaryExpressionMixin):
+class UnequalExpression(
+    VHDLModel_UnequalExpression, DOMMixin, _ParseBinaryExpressionMixin
+):
     def __init__(self, node: Iir, left: Expression, right: Expression):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
@@ -442,7 +455,11 @@ class Aggregate(VHDLModel_Aggregate, DOMMixin):
 
     @classmethod
     def parse(cls, node: Iir):
-        from pyGHDL.dom._Translate import GetExpressionFromNode, GetRangeFromNode
+        from pyGHDL.dom._Translate import (
+            GetExpressionFromNode,
+            GetRangeFromNode,
+            GetNameFromNode,
+        )
 
         choices = []
 
@@ -460,8 +477,9 @@ class Aggregate(VHDLModel_Aggregate, DOMMixin):
                 r = GetRangeFromNode(nodes.Get_Choice_Range(item))
                 choices.append(RangedAggregateElement(item, r, value))
             elif kind == nodes.Iir_Kind.Choice_By_Name:
-                name = EnumerationLiteralSymbol(item, nodes.Get_Choice_Name(item))
-                choices.append(NamedAggregateElement(item, name, value))
+                name = GetNameFromNode(nodes.Get_Choice_Name(item))
+                symbol = Symbol(item, name)
+                choices.append(NamedAggregateElement(item, symbol, value))
             elif kind == nodes.Iir_Kind.Choice_By_Others:
                 choices.append(OthersAggregateElement(item, value))
             else:
diff --git a/pyGHDL/dom/Symbol.py b/pyGHDL/dom/Symbol.py
index af6c1beb6..be8dd362e 100644
--- a/pyGHDL/dom/Symbol.py
+++ b/pyGHDL/dom/Symbol.py
@@ -39,7 +39,6 @@ from pyVHDLModel.VHDLModel import (
     SimpleSubTypeSymbol as VHDLModel_SimpleSubTypeSymbol,
     ConstrainedScalarSubTypeSymbol as VHDLModel_ConstrainedScalarSubTypeSymbol,
     ConstrainedCompositeSubTypeSymbol as VHDLModel_ConstrainedCompositeSubTypeSymbol,
-    EnumerationLiteralSymbol as VHDLModel_EnumerationLiteralSymbol,
     SimpleObjectOrFunctionCallSymbol as VHDLModel_SimpleObjectOrFunctionCallSymbol,
     IndexedObjectOrFunctionCallSymbol as VHDLModel_IndexedObjectOrFunctionCallSymbol,
     Constraint,
@@ -61,13 +60,6 @@ class EntitySymbol(VHDLModel_EntitySymbol, DOMMixin):
 
 
 @export
-class EnumerationLiteralSymbol(VHDLModel_EnumerationLiteralSymbol, DOMMixin):
-    def __init__(self, node: Iir, literalName: Name):
-        super().__init__(literalName)
-        DOMMixin.__init__(self, node)
-
-
-@export
 class SimpleSubTypeSymbol(VHDLModel_SimpleSubTypeSymbol, DOMMixin):
     def __init__(self, node: Iir, subTypeName: Name):
         if isinstance(subTypeName, (List, Iterator)):