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author | Unai Martinez-Corral <38422348+umarcor@users.noreply.github.com> | 2021-08-23 17:04:46 +0100 |
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committer | GitHub <noreply@github.com> | 2021-08-23 17:04:46 +0100 |
commit | dac2e4dca824f413821962eeac314ceaf56925a7 (patch) | |
tree | 69575b8939b2d550b7f92f0d23e4a0b854dff283 /pyGHDL/dom/Symbol.py | |
parent | 9df82e519d7e93168d43fb414c48c9e547b0c306 (diff) | |
parent | b229fa55b6485350ced8e31d6a803d08544b6d22 (diff) | |
download | ghdl-dac2e4dca824f413821962eeac314ceaf56925a7.tar.gz ghdl-dac2e4dca824f413821962eeac314ceaf56925a7.tar.bz2 ghdl-dac2e4dca824f413821962eeac314ceaf56925a7.zip |
pyGHDL: update to pyVHDLModel v0.11.5 (#1822)
New Features:
* Handle multiple identifiers in generics, ports, parameters and objects.
* `ghdl-dom` now also accepts `-D` for directories to scan.
* Resolve architectures to entities.
* Context reference
* Library clause
* Use clause
* Handle contexts of design units
* New `OpenName`
* Translate concurrent statements:
* Component instantiation
* Entity instantiation
* Configuration instantiation
* If..generate statement
* Case..generate statement
* For..generate statement
* Block statement
* Process statement
* Concurrent simple signal assignment
* Concurrent procedure call
* Translate sequential statements:
* If statement
* Case statement
* For loop
* Sequential simple signal assignment
* Sequential procedure call
* Sequential assert statement
* Sequential report statement
* Wait statement
* Print hierarchy in pretty-print
* New binding to `str_table` `string8_address`
Changes:
* Adjusted to renaming of `pyVHDLModel.VHDLModel` to `pyVHDLModel.SyntaxModel`.
* Adjust DOM to a change in pyVHDLModel: some Identifiers being now a list of identifiers.
* Reordered items in GHA workflow `Test.yml`.
* Improved ranges
Bug fixes:
* Fixed typo in IIR translation of `Greater_Than_Or_Equal_Operator`: should be `GreaterEqualExpression`.
* Wrap type marks in a `SimpleName`.
* Fixed syntax of lists in GHA workflow `Test.yml`.
* Fixed handling of bit-string literals.
Diffstat (limited to 'pyGHDL/dom/Symbol.py')
-rw-r--r-- | pyGHDL/dom/Symbol.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/pyGHDL/dom/Symbol.py b/pyGHDL/dom/Symbol.py index 3597f2572..f52afbb18 100644 --- a/pyGHDL/dom/Symbol.py +++ b/pyGHDL/dom/Symbol.py @@ -34,14 +34,14 @@ from typing import List, Iterator from pydecor import export -from pyVHDLModel.VHDLModel import ( +from pyVHDLModel.SyntaxModel import ( EntitySymbol as VHDLModel_EntitySymbol, SimpleSubtypeSymbol as VHDLModel_SimpleSubtypeSymbol, ConstrainedScalarSubtypeSymbol as VHDLModel_ConstrainedScalarSubtypeSymbol, ConstrainedCompositeSubtypeSymbol as VHDLModel_ConstrainedCompositeSubtypeSymbol, SimpleObjectOrFunctionCallSymbol as VHDLModel_SimpleObjectOrFunctionCallSymbol, IndexedObjectOrFunctionCallSymbol as VHDLModel_IndexedObjectOrFunctionCallSymbol, - Constraint, + ConstraintUnion, Name, ) from pyGHDL.libghdl._types import Iir @@ -87,7 +87,7 @@ class ConstrainedCompositeSubtypeSymbol( VHDLModel_ConstrainedCompositeSubtypeSymbol, DOMMixin ): def __init__( - self, node: Iir, subtypeName: Name, constraints: List[Constraint] = None + self, node: Iir, subtypeName: Name, constraints: List[ConstraintUnion] = None ): super().__init__(subtypeName, constraints) DOMMixin.__init__(self, node) |