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author | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2021-06-17 23:12:36 +0200 |
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committer | Unai Martinez-Corral <38422348+umarcor@users.noreply.github.com> | 2021-06-17 22:53:27 +0100 |
commit | 0c726ac36be1ad1cba24eb7eff476b9a32e643fb (patch) | |
tree | 524d81d4df412cca136b766305506574b34bf15e /pyGHDL/dom/InterfaceItem.py | |
parent | e5891f3900f5e58df37d32c2c18a0f339c094cf4 (diff) | |
download | ghdl-0c726ac36be1ad1cba24eb7eff476b9a32e643fb.tar.gz ghdl-0c726ac36be1ad1cba24eb7eff476b9a32e643fb.tar.bz2 ghdl-0c726ac36be1ad1cba24eb7eff476b9a32e643fb.zip |
Black found more files - strange.
Executed black to make code unreadable.
(cherry picked from commit 1b34c2368428b1ec295073ee47d201ac1def35f6)
Diffstat (limited to 'pyGHDL/dom/InterfaceItem.py')
-rw-r--r-- | pyGHDL/dom/InterfaceItem.py | 27 |
1 files changed, 18 insertions, 9 deletions
diff --git a/pyGHDL/dom/InterfaceItem.py b/pyGHDL/dom/InterfaceItem.py index 89427e3b4..028adc690 100644 --- a/pyGHDL/dom/InterfaceItem.py +++ b/pyGHDL/dom/InterfaceItem.py @@ -32,14 +32,17 @@ # ============================================================================ from pydecor import export -from pyVHDLModel.VHDLModel import \ - GenericConstantInterfaceItem as VHDLModel_GenericConstantInterfaceItem, \ - PortSignalInterfaceItem as VHDLModel_PortSignalInterfaceItem, \ - Mode, SubTypeOrSymbol, Expression +from pyVHDLModel.VHDLModel import ( + GenericConstantInterfaceItem as VHDLModel_GenericConstantInterfaceItem, + PortSignalInterfaceItem as VHDLModel_PortSignalInterfaceItem, + Mode, + SubTypeOrSymbol, + Expression, +) -from pyGHDL.dom._Utils import NodeToName, GetModeOfNode +from pyGHDL.dom._Utils import NodeToName, GetModeOfNode from pyGHDL.dom._Translate import GetSubtypeIndicationFromNode -from pyGHDL.dom.Common import GHDLMixin +from pyGHDL.dom.Common import GHDLMixin __all__ = [] @@ -56,10 +59,11 @@ class GenericConstantInterfaceItem(VHDLModel_GenericConstantInterfaceItem, GHDLM return generic - def __init__(self, name:str, mode: Mode, subType: SubTypeOrSymbol): + def __init__(self, name: str, mode: Mode, subType: SubTypeOrSymbol): super().__init__(name=name, mode=mode) self._subType = subType + @export class PortSignalInterfaceItem(VHDLModel_PortSignalInterfaceItem, GHDLMixin): @classmethod @@ -72,8 +76,13 @@ class PortSignalInterfaceItem(VHDLModel_PortSignalInterfaceItem, GHDLMixin): return port - def __init__(self, name:str, mode: Mode, subType: SubTypeOrSymbol, defaultExpression: Expression = None): + def __init__( + self, + name: str, + mode: Mode, + subType: SubTypeOrSymbol, + defaultExpression: Expression = None, + ): super().__init__(name=name, mode=mode) self._subType = subType self._defaultExpression = defaultExpression - |