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| author | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2021-01-04 16:07:11 +0100 |
|---|---|---|
| committer | tgingold <tgingold@users.noreply.github.com> | 2021-01-05 18:50:44 +0100 |
| commit | 29755634957933656e0e318a64bd5806b52cbf1c (patch) | |
| tree | 24afab0330dcac51e1694f55f6facbf0f6607274 /pyGHDL/dom/DesignUnit.py | |
| parent | d3ea0331006011861f539cbbaa60c8760b0fc620 (diff) | |
| download | ghdl-29755634957933656e0e318a64bd5806b52cbf1c.tar.gz ghdl-29755634957933656e0e318a64bd5806b52cbf1c.tar.bz2 ghdl-29755634957933656e0e318a64bd5806b52cbf1c.zip | |
Enabled missing Sphinx extensions. Fixed role name cls to class.
Diffstat (limited to 'pyGHDL/dom/DesignUnit.py')
| -rw-r--r-- | pyGHDL/dom/DesignUnit.py | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py index 331b2526a..40fc6796a 100644 --- a/pyGHDL/dom/DesignUnit.py +++ b/pyGHDL/dom/DesignUnit.py @@ -33,10 +33,10 @@ # ============================================================================ # """ -This module contains all DOM classes for VHDL's design units (:cls:`entity <Entity>`, -:cls:`architecture <Architecture>`, :cls:`package <Package>`, -:cls:`package body <PackageBody>`, :cls:`context <Context>` and -:cls:`configuration <Configuration>`. +This module contains all DOM classes for VHDL's design units (:class:`entity <Entity>`, +:class:`architecture <Architecture>`, :class:`package <Package>`, +:class:`package body <PackageBody>`, :class:`context <Context>` and +:class:`configuration <Configuration>`. """ @@ -58,7 +58,6 @@ from pyGHDL.dom.InterfaceItem import GenericConstantInterfaceItem, PortSignalInt __all__ = [] - @export class Entity(VHDLModel_Entity, GHDLMixin): |