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| author | Patrick Lehmann <Paebbels@gmail.com> | 2023-01-12 05:53:48 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-01-12 05:53:48 +0100 |
| commit | fb7ef864c019d325f3fc37125e6d6cdc50ae4b83 (patch) | |
| tree | 8ecca65254f939c987f182531b0cc7e13ff422b3 /pyGHDL/dom/Aggregates.py | |
| parent | 60774db2a547493b7f89de6239794b7354a0e31f (diff) | |
| download | ghdl-fb7ef864c019d325f3fc37125e6d6cdc50ae4b83.tar.gz ghdl-fb7ef864c019d325f3fc37125e6d6cdc50ae4b83.tar.bz2 ghdl-fb7ef864c019d325f3fc37125e6d6cdc50ae4b83.zip | |
Dependency Graphs (#2308)
* Further fixes to the example code.
* Bumped dependencies.
* Fixed Debouncer example code.
* Some more cleanup.
* Black's opinion.
* Run with pyVHDLModel dev-branch.
* Fixed imports for Name.
* Fixed test case.
* Added a formatter to write dependency graphs and hierarchy as graphml.
* Improved GraphML formatting.
* Write compile order graph.
* Computing compile order.
* Bumped dependencies.
* Black's opinion.
* Fixed incorrect dependency.
Diffstat (limited to 'pyGHDL/dom/Aggregates.py')
| -rw-r--r-- | pyGHDL/dom/Aggregates.py | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/pyGHDL/dom/Aggregates.py b/pyGHDL/dom/Aggregates.py index a1fe40866..968d3afc9 100644 --- a/pyGHDL/dom/Aggregates.py +++ b/pyGHDL/dom/Aggregates.py @@ -41,15 +41,14 @@ This module contains all DOM classes for VHDL's design units (:class:`context <E """ from pyTooling.Decorators import export -from pyVHDLModel.SyntaxModel import ( - SimpleAggregateElement as VHDLModel_SimpleAggregateElement, - IndexedAggregateElement as VHDLModel_IndexedAggregateElement, - RangedAggregateElement as VHDLModel_RangedAggregateElement, - NamedAggregateElement as VHDLModel_NamedAggregateElement, - OthersAggregateElement as VHDLModel_OthersAggregateElement, - ExpressionUnion, - Symbol, -) +from pyVHDLModel.Base import ExpressionUnion +from pyVHDLModel.Symbol import Symbol +from pyVHDLModel.Expression import SimpleAggregateElement as VHDLModel_SimpleAggregateElement +from pyVHDLModel.Expression import IndexedAggregateElement as VHDLModel_IndexedAggregateElement +from pyVHDLModel.Expression import RangedAggregateElement as VHDLModel_RangedAggregateElement +from pyVHDLModel.Expression import NamedAggregateElement as VHDLModel_NamedAggregateElement +from pyVHDLModel.Expression import OthersAggregateElement as VHDLModel_OthersAggregateElement + from pyGHDL.libghdl._types import Iir from pyGHDL.dom import DOMMixin from pyGHDL.dom.Range import Range |