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authorTristan Gingold <tgingold@free.fr>2020-07-28 22:31:35 +0200
committerTristan Gingold <tgingold@free.fr>2020-07-28 22:31:35 +0200
commit7fb5d5bb3939502b871ce537a2763efb9fda6926 (patch)
tree4ceae160af8caa9b8fa6ec687eedff4eb42eeb8a /libraries
parenta2ebb5ef73287c2e882f81e39a570b0e2d07150b (diff)
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openieee: add comments for divmod.
Diffstat (limited to 'libraries')
-rwxr-xr-xlibraries/openieee/build_numeric.py9
1 files changed, 6 insertions, 3 deletions
diff --git a/libraries/openieee/build_numeric.py b/libraries/openieee/build_numeric.py
index fa02580de..5eef89b2a 100755
--- a/libraries/openieee/build_numeric.py
+++ b/libraries/openieee/build_numeric.py
@@ -785,27 +785,30 @@ def disp_divmod():
-- No 'X'.
procedure divmod (num, dem : UNSIGNED; quot, remain : out UNSIGNED)
is
+ -- An extra bit is needed so that it is always possible that DEM >= REG.
variable reg : unsigned (dem'left + 1 downto 0) := (others => '0');
variable sub : unsigned (dem'range) := (others => '0');
variable carry, d : """ + logic_type () + """;
begin
for i in num'range loop
- -- Shift
+ -- Shift to add a new bit from NUM to REG.
reg (reg'left downto 1) := reg (reg'left - 1 downto 0);
reg (0) := num (i);
- -- Substract
+ -- Substract: REG - DEM
carry := '1';
for j in dem'reverse_range loop
d := not dem (j);
sub (j) := compute_sum (carry, reg (j), d);
carry := compute_carry (carry, reg (j), d);
end loop;
+ -- Do not forget the extra bit in REG.
carry := compute_carry (carry, reg (reg'left), '1');
-- Test
if carry = '0' then
- -- Greater than
+ -- REG < DEM
quot (i) := '0';
else
+ -- REG >= DEM: do the substraction
quot (i) := '1';
reg (reg'left) := '0';
reg (sub'range) := sub;