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| author | Tristan Gingold <tgingold@free.fr> | 2021-09-30 06:46:37 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-09-30 06:46:37 +0200 |
| commit | 8b49c49096b151556520897566ea2b9532b33243 (patch) | |
| tree | e5eb8c2a0eb5185873fd6b53bf83afb737aa8afd /doc | |
| parent | 1c74b6723d16f4379676dd4753c60a5268a9ae1d (diff) | |
| download | ghdl-8b49c49096b151556520897566ea2b9532b33243.tar.gz ghdl-8b49c49096b151556520897566ea2b9532b33243.tar.bz2 ghdl-8b49c49096b151556520897566ea2b9532b33243.zip | |
grt-vcd.adb: add option --vcd-4states to dump a strict vcd file. Fix #1759
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/using/Simulation.rst | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/doc/using/Simulation.rst b/doc/using/Simulation.rst index 58bfa20f2..820b90c14 100644 --- a/doc/using/Simulation.rst +++ b/doc/using/Simulation.rst @@ -279,6 +279,13 @@ Export waveforms Do not write date in the VCD file. +.. option:: --vcd-4states + + Only use the verilog states ``0/1/x/z`` to represent ``std_ulogic`` + values. The VCD file produced should be fully compatible with any + VCD reader. The default is to write ``std_ulogic`` as they are (so + keeping states ``U/W/L/H/-``), which is supported by several VCD readers. + .. option:: --fst=<FILENAME> Write the waveforms into an `fst` file. @@ -328,4 +335,4 @@ Export hierarchy and references .. option:: --psl-report-uncovered - Reports warning for each uncovered PSL cover point when simulation ends.
\ No newline at end of file + Reports warning for each uncovered PSL cover point when simulation ends. |