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| author | umarcor <unai.martinezcorral@ehu.eus> | 2022-02-07 19:28:23 +0100 |
|---|---|---|
| committer | umarcor <unai.martinezcorral@ehu.eus> | 2022-02-07 19:41:40 +0100 |
| commit | 6a694dd839a18cdf0382753fffc17aa1fbd41f9d (patch) | |
| tree | e7330a6cd6d87f80d63cc846100175b4817682bf /doc/quick_start/simulation/adder | |
| parent | ea18eb25e53567a979d40d6cc2d69e1d3e289c93 (diff) | |
| download | ghdl-6a694dd839a18cdf0382753fffc17aa1fbd41f9d.tar.gz ghdl-6a694dd839a18cdf0382753fffc17aa1fbd41f9d.tar.bz2 ghdl-6a694dd839a18cdf0382753fffc17aa1fbd41f9d.zip | |
doc: use extlinks more
Diffstat (limited to 'doc/quick_start/simulation/adder')
| -rw-r--r-- | doc/quick_start/simulation/adder/index.rst | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/doc/quick_start/simulation/adder/index.rst b/doc/quick_start/simulation/adder/index.rst index 5ff607801..693d42ef3 100644 --- a/doc/quick_start/simulation/adder/index.rst +++ b/doc/quick_start/simulation/adder/index.rst @@ -5,8 +5,8 @@ ================================= Unlike :ref:`Heartbeat <QuickStart:heartbeat>`, the target hardware design in this example is written using the -synthesisable subset of `VHDL`. It is a `full adder <https://en.wikipedia.org/wiki/Adder_(electronics)#Full_adder>`_ -described in a file named :file:`adder.vhdl`: +synthesisable subset of `VHDL`. It is a :wikipedia:`full adder <Adder_(electronics)#Full_adder>` described in a file +named :file:`adder.vhdl`: .. literalinclude:: adder.vhdl :language: vhdl |