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Move WhatIs* to About. Move About, Contributing and Copying to doc. Rename Copying to License. Append CC-BY-SA-4.0 legalcode to COPYING.md
Chapter Introduction ready for review.
Starting to rewrite Building

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diff --git a/doc/intro/Contributing.rst b/doc/intro/Contributing.rst
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-.. _INTRO:Contributing:
-
-Contributing
-############
-
-.. include:: ../shields.txt
-
-The first step might be to use GHDL and explore it's possibilities in an own project. If you are new to VHDL, see the :ref:`Quick Start Guide <USING:QuickStart>` for an introduction. Furthermore, we encourage you to read :ref:`Invoking GHDL <USING:Invoking>`, where the most commonly used options are explained. You can also check the complete :ref:`Command Reference <REF:Command>`.
-
-If you are more familiar with GHDL, you might start asking yourself how it works internally. Then, you migh find :ref:`Implementation of VHDL <REF:ImplVHDL>` and :ref:`Implementation of VITAL <REF:ImplVITAL>` interesting. 
-
-While using GHDL, you might find flaws, such as bugs, missing features, typos in the documentation or topics which are still not covered. In order to improve GHDL, we welcome bugs report and suggestions for any aspect of GHDL. So, please report them so that we are aware!
-
-Either if it's a bug or an enhancement, have a look at the |SHIELD:issues-open| and |SHIELD:issues-closed| to see if someone already told us about it. You might find a solution there. To get a broader view, you can also check the :ref:`Roadmap <CHANGE>`. Then, you can reach us through various ways:
-
-- |SHIELD:gitter|
-- Open a |SHIELD:issues-new|
-- Fork, modify and create a Pull Request on |SHIELD:issues-pr| |SHIELD:issues-pr-closed|
-- Suscribe to the mailing-list |SHIELD:mailing|
-
-The indications below shall help you choose which one to take.
-
-improve doc
-examples
-
-
-If you have an interresting project, please send us feedback or get listed on our :doc:`Who uses GHDL?` page.
-
-
-Related interesting projects
-==============
-  
-Asking for enhancements
-==============
-
-  .. _reporting_bugs:
-  
-Reporting bugs
-==============
-
-	If you cannot compile, please report the gcc version, GNAT version and gcc source version.
-	- Minimum-(non)-Working-Example (MWE)
-`How To Ask Questions The Smart Way <www.catb.org/~esr/faqs/smart-questions.html>`_
-
-If the compiler crashes, this is a bug. Reliable tools never crash.
-
-If your compiled VHDL executable crashes, this may be a bug at
-runtime or the code produced may be wrong.  However, since VHDL
-has a notion of pointers, an erroneous VHDL program (using invalid
-pointers for example) may crash.
-
-If the compiler emits an error message for a perfectly valid input or
-does not emit an error message for an invalid input, this may be a bug.
-Please send the input file and what you expected.  If you know the LRM
-well enough, please specify the paragraph which has not been well
-implemented.  If you don't know the LRM, maybe your bug report will be
-rejected simply because there is no bug.  In the latter case, it may be
-difficult to discuss the issue; and comparisons with other VHDL tools
-is not a very strong argument.
-
-If a compiler message is not clear enough for you, please tell me.  The
-error messages can be improved, but I have not enough experience with
-them.
-
-If you send a `VHDL` file producing a bug, it is a good idea to try
-to make it as short as possible.  It is also a good idea to make it
-looking like a test: write a comment which explains whether the file
-should compile, and if yes, whether or not it should run successfully.
-In the latter case, an assert statement should finish the test; the
-severity level note indicates success, while a severity level failure
-indicates failure.
-
-For bug reports, please include enough information for the maintainers to
-reproduce the problem. This includes:
-
-* the version of `GHDL` (you can get it with :samp:`ghdl --version`).
-* the operating system
-* whether you have built `GHDL` from sources or used the binary
-  distribution.
-* the content of the input files
-* a description of the problem and samples of any erroneous input
-* anything else that you think would be helpful.
-
-Documentation
-==============
-
-If you have found a mistake in the manual, please send a comment.  If
-you have not understood some parts of this manual, please tell me.
-English is not my mother tongue, so this manual may not be well-written.
-Again, rewriting part of it is a good way to improve it.
-
-.. TODO::
-
-  - Pull Requests (PRs)
-	- Check Building -> GHDL -> Directory Structure]
-	- Beware that some commit messages can `automatically close <https://help.github.com/articles/closing-issues-via-commit-messages/>`_ PRs]
-	
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diff --git a/doc/intro/Copyrights.rst b/doc/intro/Copyrights.rst
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-.. _INTRO:Copyrights:
-
-Copyrights | License
-############
-
-The GHDL front-end, the :samp:`std.textio` package and the runtime
-library (:samp:`grt`) are copyrighted Tristan Gingold, come with **absolutely
-no warranty**, and are distributed under the conditions of the General
-Public License.
-
-The :samp:`ieee.numeric_bit` and :samp:`ieee.numeric_std` packages are
-copyrighted by the IEEE.  The source files may be distributed without
-change, except as permitted by the standard.
-
-This source file may not be
-sold or distributed for profit.  See the source file and the IEEE 1076.3
-standard for more information.
-
-The :samp:`ieee.std_logic_1164`, :samp:`ieee.Math_Real` and
-:samp:`ieee.Math_Complex` packages are copyrighted by the IEEE.  See
-source files for more information.
-
-The :samp:`ieee.VITAL_Primitives`, :samp:`ieee.VITAL_Timing` and
-:samp:`ieee.VITAL_Memory` packages are copyrighted by IEEE.  See source
-file and the IEEE 1076.4 standards for more information.
-
-The packages :samp:`std_logic_arith`, 
-:samp:`std_logic_signed`, :samp:`std_logic_unsigned` and
-:samp:`std_logic_textio` contained in the :samp:`synopsys` directory are
-copyrighted by Synopsys, Inc.  The source files may be used and
-distributed without restriction provided that the copyright statements
-are not removed from the files and that any derivative work contains the
-copyright notice.  See the source files for more information.
-
-The package :samp:`std_logic_arith` contained in the :samp:`mentor`
-directory is copyrighted by Mentor Graphics.  The source files may be
-distributed in whole without restriction provided that the copyright
-statement is not removed from the file and that any derivative work
-contains this copyright notice.  See the source files for more information.
-
-As a consequence of the runtime copyright, you may not be allowed to
-distribute an executable produced by `GHDL` without the VHDL
-sources.  To my mind, this is not a real restriction, since there is no
-points in distributing VHDL executable.  Please, send a comment
-(:ref:`Reporting_bugs`) if you don't like this policy.
-
-.. TODO::
-
-  - https://www.gnu.org/licenses/old-licenses/gpl-2.0.html
-  - Available in the following formats: plain text, Texinfo, LaTeX, standalone HTML, Docbook, Markdown, ODF, RT
-  - See `#280 <https://github.com/tgingold/ghdl/issues/280#issuecomment-279595802>`_
-  
-	GHDL is copyright (c) 2002 - 2015 Tristan Gingold.
-
-	This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.
-
-	This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-
-	You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-	
-  - Contributors to ghdl:
-	- Tristan Gingold    (sole author of ghdl as a whole)
-	- Brian Drummond     (gcc4.8.2 update, OSVVM port, some bugfixes)
-	- David Koontz       (Mac OSX builds, LRM compliance work, bugfix analyses)
-	- Joris van Rantwijk (Debian packaging)
-	- Brian Davis        (Windows Mcode builds)
-	- Adam Jensen        (FreeBSD builds)
-	- Felix Bertram      (VPI interface)
-
-	with apologies to anyone who ought to be on this list but isn't. Thanks also to all those who have reported bugs and support issues, and often patches and testcases to either: https://gna.org/bugs/?group=ghdl or https://sourceforge.net/p/ghdl-updates/tickets/
-	
-	https://en.wikipedia.org/wiki/Wikipedia:Copyrights#Reusers.27_rights_and_obligations
-	https://en.wikipedia.org/wiki/Wikipedia:General_disclaimer
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diff --git a/doc/intro/WhatIsGHDL.rst b/doc/intro/WhatIsGHDL.rst
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-.. include:: <isonum.txt>
-
-.. _INTRO:GHDL:
-
-What is `GHDL`?
-###############
-
-`GHDL` is a shorthand for `G Hardware Design Language` (currently, `G` has no meaning). It is a `VHDL` compiler that can execute (nearly) any `VHDL` program. `GHDL` is *not* a synthesis tool: you cannot create a netlist with `GHDL` (yet).
-
-Unlike some other simulators, `GHDL` is a compiler: it directly translates a `VHDL` file to machine code, without using an intermediary language such as `C` or `C++`. Therefore, the compiled code should be faster and the analysis time should be shorter than with a compiler using an intermediary language.
-
-`GHDL` can use multiple back-ends, i.e. code generators, (`GCC <http://gcc.gnu.org/>`_, `LLVM <http://llvm.org/>`_ or `x86 <https://en.wikipedia.org/wiki/X86-64>`_/`i386 <https://en.wikipedia.org/wiki/Intel_80386>`_ only, a built-in one) and runs on `GNU/Linux <http://en.wikipedia.org/wiki/Linux_distribution>`_, `Windows <http://en.wikipedia.org/wiki/Microsoft_Windows>`_ |trade|  and `macOS <http://en.wikipedia.org/wiki/MacOS>`_ |trade| , both on `x86` and on `x86_64`.
-
-The current version of `GHDL` does not contain any graphical viewer: you cannot see signal waves. You can still check the behaviour of your design with a test bench. Moreover, the current version can produce a `GHW <http://ghdl.readthedocs.io/en/latest/using/Simulation.html?highlight=GHW#cmdoption-wave>`_, `VCD <https://en.wikipedia.org/wiki/Value_change_dump>`_ or `FST` files which can be viewed with a `waveform viewer <https://en.wikipedia.org/wiki/Waveform_viewer>`_, such as `GtkWave <http://gtkwave.sourceforge.net/>`_.
-
-`GHDL` aims at implementing `VHDL` as defined by `IEEE 1076 <http://ieeexplore.ieee.org/document/4772740/>`_. It supports the `1987 <http://ieeexplore.ieee.org/document/26487/>`_, `1993 <http://ieeexplore.ieee.org/document/392561/>`_ and `2002 <http://ieeexplore.ieee.org/document/1003477/>`_ revisions and, partially, the latest, `2008 <http://ieeexplore.ieee.org/document/4772740/>`_. `PSL <https://en.wikipedia.org/wiki/Property_Specification_Language>`_ is also partially supported.
-
-Several third party projects are supported: `VUnit <https://vunit.github.io/>`_, `OSVVM <http://osvvm.org/>`_, `cocotb <https://github.com/potentialventures/cocotb>`_ (through the `VPI interface <https://en.wikipedia.org/wiki/Verilog_Procedural_Interface>`_), ...
diff --git a/doc/intro/WhatIsVHDL.rst b/doc/intro/WhatIsVHDL.rst
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-.. _INTRO:VHDL:
-
-What is `VHDL`?
-###############
-
-`VHDL <https://en.wikipedia.org/wiki/VHDL>`_ is an acronym for Very High Speed Integrated Circuit (`VHSIC <https://en.wikipedia.org/wiki/VHSIC>`_) `Hardware Description Language <https://en.wikipedia.org/wiki/Hardware_description_language>`_ which is a programming language used to describe a logic circuit by function, data flow behavior, or structure.
-
-Although `VHDL` was not designed for writing general purpose programs, `VHDL` *is* a programming language, and you can write any algorithm with it. If you are able to write programs, you will find in `VHDL` features similar to those found in procedural languages such as `C`, `Python`, or `Ada`. Indeed, `VHDL` derives most of its syntax and semantics from `Ada`. Knowing `Ada` is an advantage for learning `VHDL` (it is an advantage in general as well).
-
-However, `VHDL` was not designed as a general purpose language but as an `HDL`. As the name implies, `VHDL` aims at modeling or documenting electronics systems. Due to the nature of hardware components which are always running, `VHDL` is a highly concurrent language, built upon an event-based timing model.
-
-Like a program written in any other language, a `VHDL` program can be executed. Since `VHDL` is used to model designs, the term :dfn:`simulation` is often used instead of `execution`, with the same meaning. At the same time, like a design written in another `HDL`, a set of `VHDL` sources can be transformed with a :dfn:`synthesis tool` into a netlist, that is, a detailed gate-level implementation.
-
-The development of `VHDL` started in 1983 and the standard is named `IEEE <https://www.ieee.org/>`_ `1076`. Four revisions exist: `1987 <http://ieeexplore.ieee.org/document/26487/>`_, `1993 <http://ieeexplore.ieee.org/document/392561/>`_, `2002 <http://ieeexplore.ieee.org/document/1003477/>`_ and `2008 <http://ieeexplore.ieee.org/document/4772740/>`_. The standarization is handled by the VHDL Analysis and Standardization Group (`VASG/P1076 <http://www.eda-twiki.org/vasg/>`_).