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authorumarcor <unai.martinezcorral@ehu.eus>2020-05-08 11:17:36 +0200
committertgingold <tgingold@users.noreply.github.com>2020-05-08 17:40:30 +0200
commit763e2444798682f39e1e43397b549629372b47d8 (patch)
tree70c2874844735df13a320eeb0511e42ebda6c681 /doc/examples/quick_start/adder/adder.vhdl
parent203564db51bb4db5b9009f122ac4823d6c499e9c (diff)
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doc: move 'examples/quick_start' to 'quick_start'
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-entity adder is
- -- `i0`, `i1`, and the carry-in `ci` are inputs of the adder.
- -- `s` is the sum output, `co` is the carry-out.
- port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit);
-end adder;
-
-architecture rtl of adder is
-begin
- -- This full-adder architecture contains two concurrent assignments.
- -- Compute the sum.
- s <= i0 xor i1 xor ci;
- -- Compute the carry.
- co <= (i0 and i1) or (i0 and ci) or (i1 and ci);
-end rtl;