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| author | 1138-4EB <1138-4EB@users.noreply.github.com> | 2019-11-11 18:46:36 +0000 |
|---|---|---|
| committer | tgingold <tgingold@users.noreply.github.com> | 2019-11-11 19:46:36 +0100 |
| commit | 8599d9ddd15b15afdeced6059b1e1b7a972f4db1 (patch) | |
| tree | 499b9c6fe0f85ce7ed221f72ac31036eefde0194 /doc/development/Synthesis.rst | |
| parent | 22775978be88c5ea8e5b740734e42eeb2fef0968 (diff) | |
| download | ghdl-8599d9ddd15b15afdeced6059b1e1b7a972f4db1.tar.gz ghdl-8599d9ddd15b15afdeced6059b1e1b7a972f4db1.tar.bz2 ghdl-8599d9ddd15b15afdeced6059b1e1b7a972f4db1.zip | |
Update doc (#1003)
* doc: update makefile and build scripts
* actions: add workflow 'doc'
* doc: reorganize sections
* doc: fix 'unknown option' warnings, headings, spaces, etc.
* doc: add subdir 'examples', move 'quick_start' sources
* doc: add section 'Development/Debugging'
* doc: add section'Development/Synthesis'
* doc: update roadmap
* doc: add section examples
* doc: use standard domain
* doc: add comment about 'vhd' vs 'vhdl'
Diffstat (limited to 'doc/development/Synthesis.rst')
| -rw-r--r-- | doc/development/Synthesis.rst | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/doc/development/Synthesis.rst b/doc/development/Synthesis.rst new file mode 100644 index 000000000..bcd23ff70 --- /dev/null +++ b/doc/development/Synthesis.rst @@ -0,0 +1,8 @@ +.. _DEV:Synthesis: + +Synthesis +######### + +There is an experimental command (``--synth``) to generate RTL netlists (the format, VHDL or EDIF, is yet to be defined) from synthesisable code. For command ``--synth`` to be available, GHDL must be configured/built with option ``--enable-synth`` (GCC 8.1>= required, due to some new GNAT features which are only available in recent releases). Since this is a proof-of-concept, the output is mostly a dump of an internal structure for now. Therefore, it is not very useful, except for debugging. + +Moreover, `ghdlsynth <https://github.com/tgingold/ghdlsynth-beta>`_ is a complementary repository that lets GHDL to be loaded by `yosys <http://www.clifford.at/yosys/>`_ as a frontend plugin module, in order to generate bitstreams for some FPGA devices. |