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| author | 1138-4EB <1138-4EB@users.noreply.github.com> | 2019-04-24 11:12:02 +0200 |
|---|---|---|
| committer | tgingold <tgingold@users.noreply.github.com> | 2019-04-30 19:15:34 +0200 |
| commit | 0a0fc18db7e506586e1b64fbeb9bff294425f219 (patch) | |
| tree | 0b620ce97cddf0597b22bada2d20aa8d47c749ff /doc/about.rst | |
| parent | da81679c73d79a64519b50fb40764b8d41fd6fd0 (diff) | |
| download | ghdl-0a0fc18db7e506586e1b64fbeb9bff294425f219.tar.gz ghdl-0a0fc18db7e506586e1b64fbeb9bff294425f219.tar.bz2 ghdl-0a0fc18db7e506586e1b64fbeb9bff294425f219.zip | |
update(doc)
* announce v0.36
* add hint about --synth and ghdlsynth
* add option -gGENERIC=VALUE
* add hint about --list-link
* add hint about --bind
* move 'Interfacing to other language' to it's own section
* fix shields not being shown in contribute nor in licenses
Diffstat (limited to 'doc/about.rst')
| -rw-r--r-- | doc/about.rst | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/doc/about.rst b/doc/about.rst index e1018767a..6558b77d8 100644 --- a/doc/about.rst +++ b/doc/about.rst @@ -41,6 +41,9 @@ GHDL aims at implementing VHDL as defined by `IEEE 1076 <http://ieeexplore.ieee. Several third party projects are supported: `VUnit <https://vunit.github.io/>`_, `OSVVM <http://osvvm.org/>`_, `cocotb <https://github.com/potentialventures/cocotb>`_ (through the `VPI interface <https://en.wikipedia.org/wiki/Verilog_Procedural_Interface>`_), ... +.. HINT:: + Although synthesis is not supported yet, there is some experimental code. On the one hand, subcommand ``--synth`` is a proof-of-concept to generate a netlist (RTL) with GHDL. For now, it is a dump of an internal structure, so it is not very useful, except for debugging. In the future, it might be an EDIF or VHDL file. On the other hand, `ghdlsynth <https://github.com/tgingold/ghdlsynth-beta>`_ is a complementary repository that allows GHDL to be loaded by `yosys <http://www.clifford.at/yosys/>`_ as a module, which can be used to generate bitstreams for some FPGA devices. + .. _INTRO:WHO: Who uses GHDL? |