diff options
| author | Tristan Gingold <tgingold@free.fr> | 2016-02-07 17:29:15 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2016-02-09 20:25:02 +0100 |
| commit | fa9fc93606af761b75e783390ed753f0273f24ca (patch) | |
| tree | 603db6320a6daa3106aab372f2416f1696d3400c | |
| parent | 5ddefe0ca2f02afdb7a10717b9feb77a42fbc901 (diff) | |
| download | ghdl-fa9fc93606af761b75e783390ed753f0273f24ca.tar.gz ghdl-fa9fc93606af761b75e783390ed753f0273f24ca.tar.bz2 ghdl-fa9fc93606af761b75e783390ed753f0273f24ca.zip | |
bug037: add initial testcase.
| -rw-r--r-- | testsuite/gna/bug037/arith.pkg.vhdl | 196 | ||||
| -rw-r--r-- | testsuite/gna/bug037/arith_addw.vhdl | 351 | ||||
| -rw-r--r-- | testsuite/gna/bug037/arith_addw_tb.vhdl | 153 | ||||
| -rw-r--r-- | testsuite/gna/bug037/bugreport.txt | 191 | ||||
| -rw-r--r-- | testsuite/gna/bug037/config.vhdl | 1083 | ||||
| -rw-r--r-- | testsuite/gna/bug037/my_config_ML505.vhdl | 45 | ||||
| -rw-r--r-- | testsuite/gna/bug037/my_project.vhdl | 39 | ||||
| -rw-r--r-- | testsuite/gna/bug037/physical.vhdl | 981 | ||||
| -rw-r--r-- | testsuite/gna/bug037/sim_global.v08.vhdl | 40 | ||||
| -rw-r--r-- | testsuite/gna/bug037/sim_protected.v08.vhdl | 225 | ||||
| -rw-r--r-- | testsuite/gna/bug037/sim_simulation.v08.vhdl | 440 | ||||
| -rw-r--r-- | testsuite/gna/bug037/sim_types.vhdl | 159 | ||||
| -rw-r--r-- | testsuite/gna/bug037/strings.vhdl | 936 | ||||
| -rwxr-xr-x | testsuite/gna/bug037/testsuite.sh | 22 | ||||
| -rw-r--r-- | testsuite/gna/bug037/utils.vhdl | 987 | ||||
| -rw-r--r-- | testsuite/gna/bug037/vectors.vhdl | 960 |
16 files changed, 6808 insertions, 0 deletions
diff --git a/testsuite/gna/bug037/arith.pkg.vhdl b/testsuite/gna/bug037/arith.pkg.vhdl new file mode 100644 index 000000000..bce621c6c --- /dev/null +++ b/testsuite/gna/bug037/arith.pkg.vhdl @@ -0,0 +1,196 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+--
+-- =============================================================================
+-- Authors: Thomas B. Preusser
+-- Martin Zabel
+-- Patrick Lehmann
+--
+-- Package: VHDL package for component declarations, types and functions
+-- associated to the PoC.arith namespace
+--
+-- Description:
+-- ------------------------------------
+-- For detailed documentation see below.
+--
+-- License:
+-- =============================================================================
+-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
+-- Chair for VLSI-Design, Diagnostics and Architecture
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library PoC;
+use PoC.utils.all;
+
+
+package arith is
+ component arith_firstone is
+ generic (
+ N : positive -- Length of Token Chain
+ );
+ port (
+ tin : in std_logic := '1'; -- Enable: Fed Token
+ rqst : in std_logic_vector(N-1 downto 0); -- Request: Token Requests
+ grnt : out std_logic_vector(N-1 downto 0); -- Grant: Token Output
+ tout : out std_logic; -- Inactive: Unused Token
+ bin : out std_logic_vector(log2ceil(N)-1 downto 0) -- Binary Grant Index
+ );
+ end component;
+
+ component arith_counter_bcd is
+ generic (
+ DIGITS : positive);
+ port (
+ clk : in std_logic;
+ rst : in std_logic;
+ inc : in std_logic;
+ val : out T_BCD_VECTOR(DIGITS-1 downto 0));
+ end component;
+
+ component arith_counter_gray is
+ generic (
+ BITS : positive; -- Bit width of the counter
+ INIT : natural := 0 -- Initial/reset counter value
+ );
+ port (
+ clk : in std_logic;
+ rst : in std_logic; -- Reset to INIT value
+ inc : in std_logic; -- Increment
+ dec : in std_logic := '0'; -- Decrement
+ val : out std_logic_vector(BITS-1 downto 0); -- Value output
+ cry : out std_logic -- Carry output
+ );
+ end component;
+
+ component arith_div
+ generic (
+ N : positive;
+ RAPOW : positive;
+ REGISTERED : boolean);
+ port (
+ clk : in std_logic;
+ rst : in std_logic;
+ start : in std_logic;
+ rdy : out std_logic;
+ arg1, arg2 : in std_logic_vector(N-1 downto 0);
+ res : out std_logic_vector(N-1 downto 0));
+ end component;
+
+ component arith_div_pipelined
+ generic (
+ DIVIDEND_BITS : POSITIVE;
+ DIVISOR_BITS : POSITIVE;
+ RADIX : POSITIVE
+ );
+ port (
+ Clock : in STD_LOGIC;
+ Reset : in STD_LOGIC;
+ Enable : in STD_LOGIC;
+ Dividend : in STD_LOGIC_VECTOR(DIVIDEND_BITS - 1 downto 0);
+ Divisor : in STD_LOGIC_VECTOR(DIVISOR_BITS - 1 downto 0);
+ Quotient : out STD_LOGIC_VECTOR(DIVIDEND_BITS - 1 downto 0);
+ Valid : out STD_LOGIC
+ );
+ end component;
+
+ component arith_prng
+ generic (
+ BITS : positive;
+ SEED : std_logic_vector := "0"
+ );
+ port (
+ clk : in std_logic;
+ rst : in std_logic;
+ got : in std_logic;
+ val : out std_logic_vector(BITS-1 downto 0));
+ end component;
+
+ component arith_muls_wide
+ generic (
+ NA : integer range 2 to 18;
+ NB : integer range 19 to 36;
+ SPLIT : positive
+ );
+ port (
+ a : in signed(NA-1 downto 0);
+ b : in signed(NB-1 downto 0);
+ p : out signed(NA+NB-1 downto 0)
+ );
+ end component;
+
+ component arith_sqrt
+ generic (
+ N : positive
+ );
+ port (
+ rst : in std_logic;
+ clk : in std_logic;
+ arg : in std_logic_vector(N-1 downto 0);
+ start : in std_logic;
+ sqrt : out std_logic_vector((N-1)/2 downto 0);
+ rdy : out std_logic
+ );
+ end component;
+
+ type tArch is (AAM, CAI, CCA, PAI);
+ type tBlocking is (DFLT, FIX, ASC, DESC);
+ type tSkipping is (PLAIN, CCC, PPN_KS, PPN_BK);
+
+ component arith_addw is
+ generic (
+ N : positive; -- Operand Width
+ K : positive; -- Block Count
+
+ ARCH : tArch := AAM; -- Architecture
+ BLOCKING : tBlocking := DFLT; -- Blocking Scheme
+ SKIPPING : tSkipping := CCC; -- Carry Skip Scheme
+ P_INCLUSIVE : boolean := false -- Use Inclusive Propagate, i.e. c^1
+ );
+ port (
+ a, b : in std_logic_vector(N-1 downto 0);
+ cin : in std_logic;
+
+ s : out std_logic_vector(N-1 downto 0);
+ cout : out std_logic
+ );
+ end component;
+
+ component arith_same is
+ generic (
+ N : positive -- Input width
+ );
+ port (
+ g : in std_logic := '1'; -- Guard Input (!g => !y)
+ x : in std_logic_vector(N-1 downto 0); -- Input Vector
+ y : out std_logic -- All-same Output
+ );
+ end component;
+
+ component arith_inc_ovcy_xilinx is
+ generic (
+ N : positive -- Bit Width
+ );
+ port (
+ p : in std_logic_vector(N-1 downto 0); -- Argument
+ g : in std_logic; -- Increment Guard
+ v : out std_logic -- Overflow Output
+ );
+ end component;
+end package;
diff --git a/testsuite/gna/bug037/arith_addw.vhdl b/testsuite/gna/bug037/arith_addw.vhdl new file mode 100644 index 000000000..1676a3602 --- /dev/null +++ b/testsuite/gna/bug037/arith_addw.vhdl @@ -0,0 +1,351 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+--
+-- =============================================================================
+-- Authors: Thomas B. Preusser
+--
+-- Entity: arith_addw
+--
+-- Description:
+-- ------------------------------------
+-- Implements wide addition providing several options all based
+-- on an adaptation of a carry-select approach.
+--
+-- References:
+-- * Hong Diep Nguyen and Bogdan Pasca and Thomas B. Preusser:
+-- FPGA-Specific Arithmetic Optimizations of Short-Latency Adders,
+-- FPL 2011.
+-- -> ARCH: AAM, CAI, CCA
+-- -> SKIPPING: CCC
+--
+-- * Marcin Rogawski, Kris Gaj and Ekawat Homsirikamol:
+-- A Novel Modular Adder for One Thousand Bits and More
+-- Using Fast Carry Chains of Modern FPGAs, FPL 2014.
+-- -> ARCH: PAI
+-- -> SKIPPING: PPN_KS, PPN_BK
+--
+-- License:
+-- =============================================================================
+-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
+-- Chair for VLSI-Design, Diagnostics and Architecture
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+library PoC;
+use PoC.utils.all;
+use PoC.arith.all;
+
+
+entity arith_addw is
+ generic (
+ N : positive; -- Operand Width
+ K : positive; -- Block Count
+
+ ARCH : tArch := AAM; -- Architecture
+ BLOCKING : tBlocking := DFLT; -- Blocking Scheme
+ SKIPPING : tSkipping := CCC; -- Carry Skip Scheme
+ P_INCLUSIVE : boolean := false -- Use Inclusive Propagate, i.e. c^1
+ );
+ port (
+ a, b : in std_logic_vector(N-1 downto 0);
+ cin : in std_logic;
+
+ s : out std_logic_vector(N-1 downto 0);
+ cout : out std_logic
+ );
+end entity;
+
+use std.textio.all;
+
+library IEEE;
+use IEEE.numeric_std.all;
+
+
+architecture rtl of arith_addw is
+
+ -- Determine Block Boundaries
+ type tBlocking_vector is array(tArch) of tBlocking;
+ constant DEFAULT_BLOCKING : tBlocking_vector := (AAM => ASC, CAI => DESC, PAI => DESC, CCA => DESC);
+
+ type integer_vector is array(natural range<>) of integer;
+ impure function compute_blocks return integer_vector is
+ variable bs : tBlocking := BLOCKING;
+ variable res : integer_vector(K-1 downto 0);
+
+ variable l : line;
+ begin
+ if bs = DFLT then
+ bs := DEFAULT_BLOCKING(ARCH);
+ end if;
+ case bs is
+ when FIX =>
+ assert N >= K
+ report "Cannot have more blocks than input bits."
+ severity failure;
+ for i in res'range loop
+ res(i) := ((i+1)*N+K/2)/K;
+ end loop;
+
+ when ASC =>
+ assert N-K*(K-1)/2 >= K
+ report "Too few input bits to implement growing block sizes."
+ severity failure;
+ for i in res'range loop
+ res(i) := ((i+1)*(N-K*(K-1)/2)+K/2)/K + (i+1)*i/2;
+ end loop;
+
+ when DESC =>
+ assert N-K*(K-1)/2 >= K
+ report "Too few input bits to implement growing block sizes."
+ severity failure;
+ for i in res'range loop
+ res(i) := ((i+1)*(N+K*(K-1)/2)+K/2)/K - (i+1)*i/2;
+ end loop;
+
+ when others =>
+ report "Unknown blocking scheme: "&tBlocking'image(bs) severity failure;
+
+ end case;
+ --synthesis translate_off
+ write(l, "Implementing "&integer'image(N)&"-bit wide adder: ARCH="&tArch'image(ARCH)&
+ ", BLOCKING="&tBlocking'image(bs)&'[');
+ for i in K-1 downto 1 loop
+ write(l, res(i)-res(i-1));
+ write(l, ',');
+ end loop;
+ write(l, res(0));
+ write(l, "], SKIPPING="&tSkipping'image(SKIPPING));
+ writeline(output, l);
+ --synthesis translate_on
+ return res;
+ end compute_blocks;
+ constant BLOCKS : integer_vector(K-1 downto 0) := compute_blocks;
+
+ signal g : std_logic_vector(K-1 downto 1); -- Block Generate
+ signal p : std_logic_vector(K-1 downto 1); -- Block Propagate
+ signal c : std_logic_vector(K-1 downto 1); -- Block Carry-in
+begin
+
+ -----------------------------------------------------------------------------
+ -- Rightmost Block + Carry Computation Core
+ blkCore: block
+ constant M : positive := BLOCKS(0); -- Rightmost Block Width
+ begin
+
+ -- Carry Computation with Carry Chain
+ genCCC: if SKIPPING = CCC generate
+ signal x, y : unsigned(K+M-2 downto 0);
+ signal z : unsigned(K+M-1 downto 0);
+ begin
+ x <= unsigned(g & a(M-1 downto 0));
+ genExcl: if not P_INCLUSIVE generate
+ y <= unsigned((g or p) & b(M-1 downto 0));
+ -- carry recovery for other blocks
+ c <= std_logic_vector(z(K+M-2 downto M)) xor p;
+ end generate genExcl;
+ genIncl: if P_INCLUSIVE generate
+ y <= unsigned(p & b(M-1 downto 0));
+ -- carry recovery for other blocks
+ c <= std_logic_vector(z(K+M-2 downto M)) xor (p xor g);
+ end generate genIncl;
+ z <= ('0' & x) + y + (0 to 0 => cin);
+
+ -- output of rightmost block
+ s(M-1 downto 0) <= std_logic_vector(z(M-1 downto 0));
+
+ -- carry output
+ cout <= z(z'left);
+ end generate genCCC;
+
+ -- LUT-based Carry Computations
+ genLUT: if SKIPPING /= CCC generate
+ signal z : unsigned(M downto 0);
+ begin
+ -- rightmost block
+ z <= unsigned('0' & a(M-1 downto 0)) + unsigned(b(M-1 downto 0)) + (0 to 0 => cin);
+ s(M-1 downto 0) <= std_logic_vector(z(M-1 downto 0));
+
+ -- Plain linear LUT-based Carry Forwarding
+ genPlain: if SKIPPING = PLAIN generate
+ signal t : std_logic_vector(K downto 1);
+ begin
+ -- carry forwarding
+ t(1) <= z(M);
+ t(K downto 2) <= g or (p and c);
+ c <= t(K-1 downto 1);
+ cout <= t(K);
+ end generate genPlain;
+
+ -- Kogge-Stone Parallel Prefix Network
+ genPPN_KS: if SKIPPING = PPN_KS generate
+ subtype tLevel is std_logic_vector(K-1 downto 0);
+ type tLevels is array(natural range<>) of tLevel;
+ constant LEVELS : positive := log2ceil(K);
+ signal pp, gg : tLevels(0 to LEVELS);
+ begin
+ -- carry forwarding
+ pp(0) <= p & 'X';
+ gg(0) <= g & z(M);
+ genLevels: for i in 1 to LEVELS generate
+ constant D : positive := 2**(i-1);
+ begin
+ pp(i) <= (pp(i-1)(K-1 downto D) and pp(i-1)(K-D-1 downto 0)) & pp(i-1)(D-1 downto 0);
+ gg(i) <= (gg(i-1)(K-1 downto D) or (pp(i-1)(K-1 downto D) and gg(i-1)(K-D-1 downto 0))) & gg(i-1)(D-1 downto 0);
+ end generate genLevels;
+ c <= gg(LEVELS)(K-2 downto 0);
+ cout <= gg(LEVELS)(K-1);
+ end generate genPPN_KS;
+
+ -- Brent-Kung Parallel Prefix Network
+ genPPN_BK: if SKIPPING = PPN_BK generate
+ subtype tLevel is std_logic_vector(K-1 downto 0);
+ type tLevels is array(natural range<>) of tLevel;
+ constant LEVELS : positive := log2ceil(K);
+ signal pp, gg : tLevels(0 to 2*LEVELS-1);
+ begin
+ -- carry forwarding
+ pp(0) <= p & 'X';
+ gg(0) <= g & z(M);
+ genMerge: for i in 1 to LEVELS generate
+ constant D : positive := 2**(i-1);
+ begin
+ genBits: for j in 0 to K-1 generate
+ genOp: if j mod (2*D) = 2*D-1 generate
+ gg(i)(j) <= (pp(i-1)(j) and gg(i-1)(j-D)) or gg(i-1)(j);
+ pp(i)(j) <= pp(i-1)(j) and pp(i-1)(j-D);
+ end generate;
+ genCp: if j mod (2*D) /= 2*D-1 generate
+ gg(i)(j) <= gg(i-1)(j);
+ pp(i)(j) <= pp(i-1)(j);
+ end generate;
+ end generate;
+ end generate genMerge;
+ genSpread: for i in LEVELS+1 to 2*LEVELS-1 generate
+ constant D : positive := 2**(2*LEVELS-i-1);
+ begin
+ genBits: for j in 0 to K-1 generate
+ genOp: if j > D and (j+1) mod (2*D) = D generate
+ gg(i)(j) <= (pp(i-1)(j) and gg(i-1)(j-D)) or gg(i-1)(j);
+ pp(i)(j) <= pp(i-1)(j) and pp(i-1)(j-D);
+ end generate;
+ genCp: if j <= D or (j+1) mod (2*D) /= D generate
+ gg(i)(j) <= gg(i-1)(j);
+ pp(i)(j) <= pp(i-1)(j);
+ end generate;
+ end generate;
+ end generate genSpread;
+ c <= gg(gg'high)(K-2 downto 0);
+ cout <= gg(gg'high)(K-1);
+ end generate genPPN_BK;
+
+ end generate genLUT;
+
+ end block blkCore;
+
+ -----------------------------------------------------------------------------
+ -- Implement Carry-Select Variant
+ --
+ -- all but rightmost block, implementation architecture selected by ARCH
+ genBlocks: for i in 1 to K-1 generate
+ -- Covered Index Range
+ constant LO : positive := BLOCKS(i-1); -- Low Bit Index
+ constant HI : positive := BLOCKS(i)-1; -- High Bit Index
+
+ -- Internal Block Interface
+ signal aa : unsigned(HI downto LO);
+ signal bb : unsigned(HI downto LO);
+ signal ss : unsigned(HI downto LO);
+ begin
+
+ -- Connect common block interface
+ aa <= unsigned(a(HI downto LO));
+ bb <= unsigned(b(HI downto LO));
+ s(HI downto LO) <= std_logic_vector(ss);
+
+ -- ARCH-specific Implementations
+
+ --Add-Add-Multiplex
+ genAAM: if ARCH = AAM generate
+ signal s0 : unsigned(HI+1 downto LO); -- Block Sum (cin=0)
+ signal s1 : unsigned(HI+1 downto LO); -- Block Sum (cin=1)
+ begin
+ s0 <= ('0' & aa) + bb;
+ s1 <= ('0' & aa) + bb + 1;
+ g(i) <= s0(HI+1);
+ genExcl: if not P_INCLUSIVE generate
+ p(i) <= s1(HI+1) xor s0(HI+1);
+ end generate genExcl;
+ genIncl: if P_INCLUSIVE generate
+ p(i) <= s1(HI+1);
+ end generate genIncl;
+
+ ss <= s0(HI downto LO) when c(i) = '0' else s1(HI downto LO);
+ end generate genAAM;
+
+ -- Compare-Add-Increment
+ genCAI: if ARCH = CAI generate
+ signal s0 : unsigned(HI+1 downto LO); -- Block Sum (cin=0)
+ begin
+ s0 <= ('0' & aa) + bb;
+ g(i) <= s0(HI+1);
+ genExcl: if not P_INCLUSIVE generate
+ p(i) <= 'X' when Is_X(std_logic_vector(aa&bb)) else
+ '1' when (aa xor bb) = (aa'range => '1') else '0';
+ end generate genExcl;
+ genIncl: if P_INCLUSIVE generate
+ p(i) <= 'X' when Is_X(std_logic_vector(aa&bb)) else
+ '1' when aa >= not bb else '0';
+ end generate genIncl;
+ ss <= s0(HI downto LO) when c(i) = '0' else s0(HI downto LO)+1;
+ end generate genCAI;
+
+ -- Propagate-Add-Increment
+ genPAI: if ARCH = PAI generate
+ signal s0 : unsigned(HI+1 downto LO); -- Block Sum (cin=0)
+ begin
+ s0 <= ('0' & aa) + bb;
+ g(i) <= s0(HI+1);
+ genExcl: if not P_INCLUSIVE generate
+ p(i) <= 'X' when Is_X(std_logic_vector(s0)) else
+ '1' when s0(HI downto LO) = (HI downto LO => '1') else '0';
+ end generate genExcl;
+ genIncl: if P_INCLUSIVE generate
+ p(i) <= 'X' when Is_X(std_logic_vector(s0)) else
+ '1' when s0(HI downto LO) = (HI downto LO => '1') else g(i);
+ end generate genIncl;
+ ss <= s0(HI downto LO) when c(i) = '0' else s0(HI downto LO)+1;
+ end generate genPAI;
+
+ -- Compare-Compare-Add
+ genCCA: if ARCH = CCA generate
+ g(i) <= 'X' when Is_X(std_logic_vector(aa&bb)) else
+ '1' when aa > not bb else '0';
+ genExcl: if not P_INCLUSIVE generate
+ p(i) <= 'X' when Is_X(std_logic_vector(aa&bb)) else
+ '1' when (aa xor bb) = (aa'range => '1') else '0';
+ end generate genExcl;
+ genIncl: if P_INCLUSIVE generate
+ p(i) <= 'X' when Is_X(std_logic_vector(aa&bb)) else
+ '1' when aa >= not bb else '0';
+ end generate genIncl;
+ ss <= aa + bb + (0 to 0 => c(i));
+ end generate genCCA;
+
+ end generate genBlocks;
+
+end architecture;
diff --git a/testsuite/gna/bug037/arith_addw_tb.vhdl b/testsuite/gna/bug037/arith_addw_tb.vhdl new file mode 100644 index 000000000..17dad7235 --- /dev/null +++ b/testsuite/gna/bug037/arith_addw_tb.vhdl @@ -0,0 +1,153 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+--
+-- ============================================================================
+-- Authors: Thomas B. Preusser
+--
+-- Testbench: arith_addw_tb
+--
+-- Description:
+-- ------------
+-- Testbench for arith_addw.
+--
+-- License:
+-- ============================================================================
+-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
+-- Chair for VLSI-Design, Diagnostics and Architecture
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library PoC;
+use PoC.strings.all;
+use PoC.physical.all;
+use PoC.arith.all;
+-- simulation only packages
+use PoC.sim_global.all;
+use PoC.sim_types.all;
+use PoC.simulation.all;
+
+
+entity arith_addw_tb is
+end entity;
+
+
+architecture tb of arith_addw_tb is
+ constant CLOCK_FREQ : FREQ := 100 MHz;
+
+ -- component generics
+ constant N : positive := 9;
+ constant K : positive := 2;
+
+ subtype tArch_test is tArch;
+ subtype tSkip_test is tSkipping;
+
+ -- component ports
+ subtype word is std_logic_vector(N-1 downto 0);
+ type word_vector is array(tArch_test, tSkip_test, boolean) of word;
+ type carry_vector is array(tArch_test, tSkip_test, boolean) of std_logic;
+
+ signal Clock : STD_LOGIC;
+ signal a, b : word;
+ signal cin : std_logic;
+ signal s : word_vector;
+ signal cout : carry_vector;
+
+begin
+ -- initialize global simulation status
+ simInitialize;
+
+ -- generate global testbench clock
+ simGenerateClock(Clock, CLOCK_FREQ);
+
+ -- DUTs
+ genArchs: for i in tArch_test generate
+ genSkips: for j in tSkip_test generate
+ genIncl: for p in false to true generate
+ constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup: " &
+ "ARCH=" & str_lalign(TARCH'image(i), 5) &
+ "SKIPPING=" & str_lalign(TSKIPPING'image(j), 8) &
+ "P_INCLUSIVE=" & str_lalign(BOOLEAN'image(p), 7));
+ begin
+ DUT : entity PoC.arith_addw
+ generic map (
+ N => N,
+ K => K,
+ ARCH => i,
+ SKIPPING => j,
+ P_INCLUSIVE => p
+ )
+ port map (
+ a => a,
+ b => b,
+ cin => cin,
+ s => s(i, j, p),
+ cout => cout(i, j, p)
+ );
+ end generate genIncl;
+ end generate;
+ end generate;
+
+ -- Stimuli
+ procChecker : process
+ -- from Simulation
+ constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Combined Generator and Checker"); --, "aaa/bbb/ccc"); --globalSimulationStatus'instance_name);
+
+ begin
+ for i in natural range 0 to 2**N-1 loop
+ a <= std_logic_vector(to_unsigned(i, N));
+ for j in natural range 0 to 2**N-1 loop
+ b <= std_logic_vector(to_unsigned(j, N));
+
+ cin <= '0';
+ wait until rising_edge(Clock);
+ for arch in tArch_test loop
+ for skip in tSkip_test loop
+ for incl in boolean loop
+ simAssertion((i+j) mod 2**(N+1) = to_integer(unsigned(cout(arch, skip, incl) & s(arch, skip, incl))),
+ "Output Error["&tArch'image(arch)&','&tSkipping'image(skip)&','&boolean'image(incl)&"]: "&
+ integer'image(i)&'+'&integer'image(j)&" != "&
+ integer'image(to_integer(unsigned(cout(arch, skip, incl) & s(arch, skip, incl)))));
+ end loop;
+ end loop;
+ end loop;
+
+ cin <= '1';
+ wait until falling_edge(Clock);
+ for arch in tArch_test loop
+ for skip in tSkip_test loop
+ for incl in boolean loop
+ simAssertion((i+j+1) mod 2**(N+1) = to_integer(unsigned(cout(arch, skip, incl) & s(arch, skip, incl))),
+ "Output Error["&tArch'image(arch)&','&tSkipping'image(skip)&','&boolean'image(incl)&"]: "&
+ integer'image(i)&'+'&integer'image(j)&"+1 != "&
+ integer'image(to_integer(unsigned(cout(arch, skip, incl) & s(arch, skip, incl)))));
+ end loop;
+ end loop;
+ end loop;
+
+ end loop; -- j
+ end loop; -- i
+
+ -- This process is finished
+ simDeactivateProcess(simProcessID);
+ -- Report overall result
+ simFinalize;
+ wait; -- forever
+ end process;
+
+end architecture;
diff --git a/testsuite/gna/bug037/bugreport.txt b/testsuite/gna/bug037/bugreport.txt new file mode 100644 index 000000000..0f61af22e --- /dev/null +++ b/testsuite/gna/bug037/bugreport.txt @@ -0,0 +1,191 @@ +#
+# Bug report created by PoC
+#
+# Assemble files for the bug report....
+# execute these lines in PowerShell to gather all needed files
+#
+mkdir H:\Austausch\PoC\temp\bugreport | cd
+cp H:\Austausch\PoC\tb\common\my_config_ML505.vhdl .
+cp H:\Austausch\PoC\tb\common\my_project.vhdl .
+cp H:\Austausch\PoC\src\common\utils.vhdl .
+cp H:\Austausch\PoC\src\common\config.vhdl .
+cp H:\Austausch\PoC\src\common\strings.vhdl .
+cp H:\Austausch\PoC\src\common\vectors.vhdl .
+cp H:\Austausch\PoC\src\common\physical.vhdl .
+cp H:\Austausch\PoC\src\sim\sim_types.vhdl .
+cp H:\Austausch\PoC\src\sim\sim_protected.v08.vhdl .
+cp H:\Austausch\PoC\src\sim\sim_global.v08.vhdl .
+cp H:\Austausch\PoC\src\sim\sim_simulation.v08.vhdl .
+cp H:\Austausch\PoC\src\arith\arith.pkg.vhdl .
+cp H:\Austausch\PoC\src\arith\arith_addw.vhdl .
+cp H:\Austausch\PoC\tb\arith\arith_addw_tb.vhdl .
+
+
+#
+# ATTENATION: This test requires Xilinx ISE unisim compiled into the folder ./xilinx
+#
+ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./my_config_ML505.vhdl
+ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./my_project.vhdl
+ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./utils.vhdl
+ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./config.vhdl
+ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./strings.vhdl
+ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./vectors.vhdl
+ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./physical.vhdl
+ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./sim_types.vhdl
+ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./sim_protected.v08.vhdl
+ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./sim_global.v08.vhdl
+ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./sim_simulation.v08.vhdl
+ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./arith.pkg.vhdl
+ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./arith_addw.vhdl
+ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=test ./arith_addw_tb.vhdl
+
+# excepted runtime circa 2 minutes
+ghdl.exe -r --syn-binding -fpsl -v -Pxilinx --std=08 --work=test arith_addw_tb --ieee-asserts=disable-at-0 --wave=H:\Austausch\PoC\temp\ghdl\arith_addw_tb.ghw
+
+# Generated output
+--------------------------------------------------------------------------------
+Linking in memory
+Starting simulation
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ppn_bk
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ppn_bk
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ppn_bk
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ppn_bk
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ppn_bk
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ppn_bk
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ppn_bk
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ppn_bk
+
+******************** GHDL Bug occured ****************************
+Please report this bug on https://github.com/tgingold/ghdl/issues
+GHDL release: GHDL 0.34dev (commit: 2016-01-20; git branch: paebbels/llvm'; hash: 3a8fd5b) [Dunoon edition]
+Compiled with GNAT Version: GPL 2015 (20150428-49)
+In directory: H:\Austausch\PoC\temp\ghdl\
+Command line:
+C:\Tools\GHDL.new\bin\ghdl.exe -r --syn-binding -fpsl -v -Pxilinx --std=08 --work=test arith_addw_tb --ieee-asserts=disable-at-0 --wave=H:\Austausch\PoC\temp\ghdl\arith_addw_tb.ghw
+Exception CONSTRAINT_ERROR raised
+Exception information:
+Exception name: CONSTRAINT_ERROR
+Message: grt-waves.adb:1245 access check failed
+******************************************************************
+
+--------------------------------------------------------------------------------
+#
+#
+# Expected Output
+#
+
+--------------------------------------------------------------------------------
+Linking in memory
+Starting simulation
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ppn_bk
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ppn_bk
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ppn_bk
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ppn_bk
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ppn_bk
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ppn_bk
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ppn_bk
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ppn_bk
+H:\Austausch\PoC\src\sim\sim_simulation.v08.vhdl:232:16:@0ms:(report note): simGenerateClock: (Instance: ':poc:simulation:simgenerateclock[std_logic,time,t_phase,t_dutycycle,t_wander]:clock')
+Period: 10000000 fs
+Phase: 0 second
+DutyCycle: 500000000 ppb
+PhaseAsFactor: 0.0
+WanderAsFactor: 0.0
+DutyCycleAsFactor: 5.0e-1
+Delay: 0 fs
+TimeHigh: 5000000 fs
+TimeLow: 5000000 fs
+
+========================================
+POC TESTBENCH REPORT
+========================================
+Assertions 16777216
+ failed 0
+Processes 1
+ active 0
+Tests 32
+ 0: Test setup: ARCH=aam SKIPPING=plain P_INCLUSIVE=false
+ 1: Test setup: ARCH=aam SKIPPING=plain P_INCLUSIVE=true
+ 2: Test setup: ARCH=aam SKIPPING=ccc P_INCLUSIVE=false
+ 3: Test setup: ARCH=aam SKIPPING=ccc P_INCLUSIVE=true
+ 4: Test setup: ARCH=aam SKIPPING=ppn_ks P_INCLUSIVE=false
+ 5: Test setup: ARCH=aam SKIPPING=ppn_ks P_INCLUSIVE=true
+ 6: Test setup: ARCH=aam SKIPPING=ppn_bk P_INCLUSIVE=false
+ 7: Test setup: ARCH=aam SKIPPING=ppn_bk P_INCLUSIVE=true
+ 8: Test setup: ARCH=cai SKIPPING=plain P_INCLUSIVE=false
+ 9: Test setup: ARCH=cai SKIPPING=plain P_INCLUSIVE=true
+ 10: Test setup: ARCH=cai SKIPPING=ccc P_INCLUSIVE=false
+ 11: Test setup: ARCH=cai SKIPPING=ccc P_INCLUSIVE=true
+ 12: Test setup: ARCH=cai SKIPPING=ppn_ks P_INCLUSIVE=false
+ 13: Test setup: ARCH=cai SKIPPING=ppn_ks P_INCLUSIVE=true
+ 14: Test setup: ARCH=cai SKIPPING=ppn_bk P_INCLUSIVE=false
+ 15: Test setup: ARCH=cai SKIPPING=ppn_bk P_INCLUSIVE=true
+ 16: Test setup: ARCH=cca SKIPPING=plain P_INCLUSIVE=false
+ 17: Test setup: ARCH=cca SKIPPING=plain P_INCLUSIVE=true
+ 18: Test setup: ARCH=cca SKIPPING=ccc P_INCLUSIVE=false
+ 19: Test setup: ARCH=cca SKIPPING=ccc P_INCLUSIVE=true
+ 20: Test setup: ARCH=cca SKIPPING=ppn_ks P_INCLUSIVE=false
+ 21: Test setup: ARCH=cca SKIPPING=ppn_ks P_INCLUSIVE=true
+ 22: Test setup: ARCH=cca SKIPPING=ppn_bk P_INCLUSIVE=false
+ 23: Test setup: ARCH=cca SKIPPING=ppn_bk P_INCLUSIVE=true
+ 24: Test setup: ARCH=pai SKIPPING=plain P_INCLUSIVE=false
+ 25: Test setup: ARCH=pai SKIPPING=plain P_INCLUSIVE=true
+ 26: Test setup: ARCH=pai SKIPPING=ccc P_INCLUSIVE=false
+ 27: Test setup: ARCH=pai SKIPPING=ccc P_INCLUSIVE=true
+ 28: Test setup: ARCH=pai SKIPPING=ppn_ks P_INCLUSIVE=false
+ 29: Test setup: ARCH=pai SKIPPING=ppn_ks P_INCLUSIVE=true
+ 30: Test setup: ARCH=pai SKIPPING=ppn_bk P_INCLUSIVE=false
+ 31: Test setup: ARCH=pai SKIPPING=ppn_bk P_INCLUSIVE=true
+========================================
+SIMULATION RESULT = PASSED
+========================================
+
+--------------------------------------------------------------------------------
diff --git a/testsuite/gna/bug037/config.vhdl b/testsuite/gna/bug037/config.vhdl new file mode 100644 index 000000000..4caa1022e --- /dev/null +++ b/testsuite/gna/bug037/config.vhdl @@ -0,0 +1,1083 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+--
+-- ============================================================================
+-- Authors: Thomas B. Preusser
+-- Martin Zabel
+-- Patrick Lehmann
+--
+-- Package: Global configuration settings.
+--
+-- Description:
+-- ------------------------------------
+-- This file evaluates the settings declared in the project specific package my_config.
+-- See also template file my_config.vhdl.template.
+--
+-- License:
+-- ============================================================================
+-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
+-- Chair for VLSI-Design, Diagnostics and Architecture
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- ============================================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library PoC;
+use PoC.utils.all;
+
+package config_private is
+ -- TODO:
+ -- ===========================================================================
+ subtype T_BOARD_STRING is STRING(1 to 16);
+ subtype T_BOARD_CONFIG_STRING is STRING(1 to 64);
+ subtype T_DEVICE_STRING is STRING(1 to 32);
+
+ -- Data structures to describe UART / RS232
+ type T_BOARD_UART_DESC is record
+ IsDTE : BOOLEAN; -- Data terminal Equipment (e.g. PC, Printer)
+ FlowControl : T_BOARD_CONFIG_STRING; -- (NONE, SW, HW_CTS_RTS, HW_RTR_RTS)
+ BaudRate : T_BOARD_CONFIG_STRING; -- e.g. "115.2 kBd"
+ BaudRate_Max : T_BOARD_CONFIG_STRING;
+ end record;
+
+ -- Data structures to describe Ethernet
+ type T_BOARD_ETHERNET_DESC is record
+ IPStyle : T_BOARD_CONFIG_STRING;
+ RS_DataInterface : T_BOARD_CONFIG_STRING;
+ PHY_Device : T_BOARD_CONFIG_STRING;
+ PHY_DeviceAddress : STD_LOGIC_VECTOR(7 downto 0);
+ PHY_DataInterface : T_BOARD_CONFIG_STRING;
+ PHY_ManagementInterface : T_BOARD_CONFIG_STRING;
+ end record;
+
+ subtype T_BOARD_ETHERNET_DESC_INDEX is NATURAL range 0 to 7;
+ type T_BOARD_ETHERNET_DESC_VECTOR is array(NATURAL range <>) of T_BOARD_ETHERNET_DESC;
+
+ -- Data structures to describe a board layout
+ type T_BOARD_INFO is record
+ BoardName : T_BOARD_CONFIG_STRING;
+ FPGADevice : T_BOARD_CONFIG_STRING;
+ UART : T_BOARD_UART_DESC;
+ Ethernet : T_BOARD_ETHERNET_DESC_VECTOR(T_BOARD_ETHERNET_DESC_INDEX);
+ EthernetCount : T_BOARD_ETHERNET_DESC_INDEX;
+ end record;
+
+ type T_BOARD_INFO_VECTOR is array (natural range <>) of T_BOARD_INFO;
+
+ constant C_POC_NUL : CHARACTER;
+ constant C_BOARD_STRING_EMPTY : T_BOARD_STRING;
+ constant C_BOARD_CONFIG_STRING_EMPTY : T_BOARD_CONFIG_STRING;
+ constant C_DEVICE_STRING_EMPTY : T_DEVICE_STRING;
+ CONSTANT C_BOARD_INFO_LIST : T_BOARD_INFO_VECTOR;
+
+ function conf(str : string) return T_BOARD_CONFIG_STRING;
+end package;
+
+
+package body config_private is
+ constant C_POC_NUL : CHARACTER := '~';
+ constant C_BOARD_STRING_EMPTY : T_BOARD_STRING := (others => C_POC_NUL);
+ constant C_BOARD_CONFIG_STRING_EMPTY : T_BOARD_CONFIG_STRING := (others => C_POC_NUL);
+ constant C_DEVICE_STRING_EMPTY : T_DEVICE_STRING := (others => C_POC_NUL);
+
+ function conf(str : string) return T_BOARD_CONFIG_STRING is
+ constant ConstNUL : STRING(1 to 1) := (others => C_POC_NUL);
+ variable Result : STRING(1 to T_BOARD_CONFIG_STRING'length);
+ begin
+ Result := (others => C_POC_NUL);
+ if (str'length > 0) then
+ Result(1 to imin(T_BOARD_CONFIG_STRING'length, imax(1, str'length))) := ite((str'length > 0), str(1 to imin(T_BOARD_CONFIG_STRING'length, str'length)), ConstNUL);
+ end if;
+ return Result;
+ end function;
+
+ constant C_BOARD_ETHERNET_DESC_EMPTY : T_BOARD_ETHERNET_DESC := (
+ IPStyle => C_BOARD_CONFIG_STRING_EMPTY,
+ RS_DataInterface => C_BOARD_CONFIG_STRING_EMPTY,
+ PHY_Device => C_BOARD_CONFIG_STRING_EMPTY,
+ PHY_DeviceAddress => x"00",
+ PHY_DataInterface => C_BOARD_CONFIG_STRING_EMPTY,
+ PHY_ManagementInterface => C_BOARD_CONFIG_STRING_EMPTY
+ );
+
+ -- predefined UART descriptions
+ function brd_CreateUART(IsDTE : BOOLEAN; FlowControl : STRING; BaudRate : STRING; BaudRate_Max : STRING := "") return T_BOARD_UART_DESC is
+ variable Result : T_BOARD_UART_DESC;
+ begin
+ Result.IsDTE := IsDTE;
+ Result.FlowControl := conf(FlowControl);
+ Result.BaudRate := conf(BaudRate);
+ Result.BaudRate_Max := ite((BaudRate_Max = ""), conf(BaudRate), conf(BaudRate_Max));
+ return Result;
+ end function;
+
+ -- IsDTE FlowControl BaudRate
+ constant C_BOARD_UART_EMPTY : T_BOARD_UART_DESC := brd_CreateUART(TRUE, "NONE", "0 Bd");
+ constant C_BOARD_UART_DTE_115200_NONE : T_BOARD_UART_DESC := brd_CreateUART(TRUE, "NONE", "115.2 kBd");
+ constant C_BOARD_UART_DCE_115200_NONE : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "NONE", "115.2 kBd");
+ constant C_BOARD_UART_DCE_115200_HWCTS : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "HW_CTS_RTS", "115.2 kBd");
+ constant C_BOARD_UART_DCE_460800_NONE : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "NONE", "460.8 kBd");
+ constant C_BOARD_UART_DTE_921600_NONE : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "NONE", "921.6 kBd");
+
+ function brd_CreateEthernet(IPStyle : STRING; RS_DataInt : STRING; PHY_Device : STRING; PHY_DevAddress : STD_LOGIC_VECTOR(7 downto 0); PHY_DataInt : STRING; PHY_MgntInt : STRING) return T_BOARD_ETHERNET_DESC is
+ variable Result : T_BOARD_ETHERNET_DESC;
+ begin
+ Result.IPStyle := conf(IPStyle);
+ Result.RS_DataInterface := conf(RS_DataInt);
+ Result.PHY_Device := conf(PHY_Device);
+ Result.PHY_DeviceAddress := PHY_DevAddress;
+ Result.PHY_DataInterface := conf(PHY_DataInt);
+ Result.PHY_ManagementInterface := conf(PHY_MgntInt);
+ return Result;
+ end function;
+
+ constant C_BOARD_ETH_EMPTY : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("", "", "", x"00", "", "");
+ constant C_BOARD_ETH_SOFT_GMII_88E1111 : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"07", "GMII", "MDIO");
+ constant C_BOARD_ETH_HARD_GMII_88E1111 : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("HARD", "GMII", "MARVEL_88E1111", x"07", "GMII", "MDIO");
+ constant C_BOARD_ETH_SOFT_SGMII_88E1111 : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"07", "SGMII", "MDIO_OVER_IIC");
+
+ constant C_BOARD_ETH_NONE : T_BOARD_ETHERNET_DESC_VECTOR(T_BOARD_ETHERNET_DESC_INDEX) := (others => C_BOARD_ETH_EMPTY);
+
+
+ -- Board Descriptions
+ -- ===========================================================================
+ CONSTANT C_BOARD_INFO_LIST : T_BOARD_INFO_VECTOR := (
+ -- Altera boards
+ -- =========================================================================
+ (
+ BoardName => conf("DE0"),
+ FPGADevice => conf("EP3C16F484"), -- EP3C16F484
+ UART => C_BOARD_UART_EMPTY,
+ Ethernet => C_BOARD_ETH_NONE,
+ EthernetCount => 0
+ ),(
+ BoardName => conf("S2GXAV"),
+ FPGADevice => conf("EP2SGX90FF1508C3"), -- EP2SGX90FF1508C3
+ UART => C_BOARD_UART_EMPTY,
+ Ethernet => C_BOARD_ETH_NONE,
+ EthernetCount => 0
+ ),(
+ BoardName => conf("DE4"),
+ FPGADevice => conf("EP4SGX230KF40C2"), -- EP4SGX230KF40C2
+ UART => C_BOARD_UART_DCE_460800_NONE,
+ Ethernet => (
+ 0 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"00", "RGMII", "MDIO"),
+ 1 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"01", "RGMII", "MDIO"),
+ 2 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"02", "RGMII", "MDIO"),
+ 3 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"03", "RGMII", "MDIO"),
+ others => C_BOARD_ETH_EMPTY
+ ),
+ EthernetCount => 4
+ ),(
+ BoardName => conf("DE5"),
+ FPGADevice => conf("EP5SGXEA7N2F45C2"), -- EP5SGXEA7N2F45C2
+ UART => C_BOARD_UART_EMPTY,
+ Ethernet => C_BOARD_ETH_NONE,
+ EthernetCount => 0
+ ),
+ -- Lattice boards
+ -- =========================================================================
+ (
+ BoardName => conf("ECP5 Versa"),
+ FPGADevice => conf("LFE5UM-45F-6BG381C"), -- LFE5UM-45F-6BG381C
+ UART => C_BOARD_UART_EMPTY,
+ Ethernet => C_BOARD_ETH_NONE,
+ EthernetCount => 0
+ ),
+ -- Xilinx boards
+ -- =========================================================================
+ (
+ BoardName => conf("S3SK200"),
+ FPGADevice => conf("XC3S200FT256"), -- XC2S200FT256
+ UART => C_BOARD_UART_EMPTY,
+ Ethernet => C_BOARD_ETH_NONE,
+ EthernetCount => 0
+ ),(
+ BoardName => conf("S3SK1000"),
+ FPGADevice => conf("XC3S1000FT256"), -- XC2S200FT256
+ UART => C_BOARD_UART_EMPTY,
+ Ethernet => C_BOARD_ETH_NONE,
+ EthernetCount => 0
+ ),(
+ BoardName => conf("S3ESK500"),
+ FPGADevice => conf("XC3S500EFT256"), -- XC2S200FT256
+ UART => C_BOARD_UART_EMPTY,
+ Ethernet => C_BOARD_ETH_NONE,
+ EthernetCount => 0
+ ),(
+ BoardName => conf("S3ESK1600"),
+ FPGADevice => conf("XC3S1600EFT256"), -- XC2S200FT256
+ UART => C_BOARD_UART_EMPTY,
+ Ethernet => C_BOARD_ETH_NONE,
+ EthernetCount => 0
+ ),(
+ BoardName => conf("ATLYS"),
+ FPGADevice => conf("XC6SLX45-3CSG324"), -- XC6SLX45-3CSG324
+ UART => C_BOARD_UART_DCE_460800_NONE,
+ Ethernet => (
+ 0 => C_BOARD_ETH_HARD_GMII_88E1111,
+ others => C_BOARD_ETH_EMPTY),
+ EthernetCount => 1
+ ),(
+ BoardName => conf("ZC706"),
+ FPGADevice => conf("XC7Z045-2FFG900"), -- XC7K325T-2FFG900C
+ UART => C_BOARD_UART_DTE_921600_NONE,
+ Ethernet => C_BOARD_ETH_NONE,
+ EthernetCount => 0
+ ),(
+ BoardName => conf("KC705"),
+ FPGADevice => conf("XC7K325T-2FFG900C"), -- XC7K325T-2FFG900C
+ UART => C_BOARD_UART_DTE_921600_NONE,
+ Ethernet => (
+ 0 => C_BOARD_ETH_SOFT_GMII_88E1111,
+ others => C_BOARD_ETH_EMPTY),
+ EthernetCount => 1
+ ),(
+ BoardName => conf("ML505"),
+ FPGADevice => conf("XC5VLX50T-1FF1136"), -- XC5VLX50T-1FF1136
+ UART => C_BOARD_UART_DCE_115200_NONE,
+ Ethernet => (
+ 0 => C_BOARD_ETH_HARD_GMII_88E1111,
+ others => C_BOARD_ETH_EMPTY),
+ EthernetCount => 1
+ ),(
+ BoardName => conf("ML506"),
+ FPGADevice => conf("XC5VSX50T-1FFG1136"), -- XC5VSX50T-1FFG1136
+ UART => C_BOARD_UART_DCE_115200_NONE,
+ Ethernet => (
+ 0 => C_BOARD_ETH_HARD_GMII_88E1111,
+ others => C_BOARD_ETH_EMPTY),
+ EthernetCount => 1
+ ),(
+ BoardName => conf("ML507"),
+ FPGADevice => conf("XC5VFX70T-1FFG1136"), -- XC5VFX70T-1FFG1136
+ UART => C_BOARD_UART_DCE_115200_NONE,
+ Ethernet => (
+ 0 => C_BOARD_ETH_HARD_GMII_88E1111,
+ others => C_BOARD_ETH_EMPTY),
+ EthernetCount => 1
+ ),(
+ BoardName => conf("XUPV5"),
+ FPGADevice => conf("XC5VLX110T-1FF1136"), -- XC5VLX110T-1FF1136
+ UART => C_BOARD_UART_DCE_115200_NONE,
+ Ethernet => (
+ 0 => C_BOARD_ETH_HARD_GMII_88E1111,
+ others => C_BOARD_ETH_EMPTY),
+ EthernetCount => 1
+ ),(
+ BoardName => conf("ML605"),
+ FPGADevice => conf("XC6VLX240T-1FF1156"), -- XC6VLX240T-1FF1156
+ UART => C_BOARD_UART_EMPTY,
+ Ethernet => (
+ 0 => C_BOARD_ETH_HARD_GMII_88E1111,
+ others => C_BOARD_ETH_EMPTY),
+ EthernetCount => 1
+ ),(
+ BoardName => conf("VC707"),
+ FPGADevice => conf("XC7VX485T-2FFG1761C"), -- XC7VX485T-2FFG1761C
+ UART => C_BOARD_UART_DTE_921600_NONE,
+ Ethernet => (
+ 0 => C_BOARD_ETH_SOFT_SGMII_88E1111,
+ others => C_BOARD_ETH_EMPTY),
+ EthernetCount => 1
+ ),(
+ BoardName => conf("VC709"),
+ FPGADevice => conf("XC7VX690T-2FFG1761C"), -- XC7VX690T-2FFG1761C
+ UART => C_BOARD_UART_DTE_921600_NONE,
+ Ethernet => C_BOARD_ETH_NONE,
+ EthernetCount => 0
+ ),(
+ BoardName => conf("ZEDBOARD"),
+ FPGADevice => conf("XC7Z020-1CLG484"), -- XC7Z020-1CLG484
+ UART => C_BOARD_UART_EMPTY,
+ Ethernet => C_BOARD_ETH_NONE,
+ EthernetCount => 0
+ ),
+ -- Custom Board (MUST BE LAST ONE)
+ -- =========================================================================
+ (
+ BoardName => conf("Custom"),
+ FPGADevice => conf("Device is unknown for a custom board"),
+ UART => C_BOARD_UART_EMPTY,
+ Ethernet => C_BOARD_ETH_NONE,
+ EthernetCount => 0
+ )
+ );
+end package body;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library PoC;
+use PoC.my_config.all;
+use PoC.my_project.all;
+use PoC.config_private.all;
+use PoC.utils.all;
+
+
+package config is
+ constant PROJECT_DIR : string := MY_PROJECT_DIR;
+ constant OPERATING_SYSTEM : string := MY_OPERATING_SYSTEM;
+
+ -- List of known FPGA / Chip vendors
+ -- ---------------------------------------------------------------------------
+ type T_VENDOR is (
+ VENDOR_UNKNOWN,
+ VENDOR_ALTERA,
+ VENDOR_LATTICE,
+ VENDOR_XILINX
+ );
+
+ -- List of known synthesis tool chains
+ -- ---------------------------------------------------------------------------
+ type T_SYNTHESIS_TOOL is (
+ SYNTHESIS_TOOL_UNKNOWN,
+ SYNTHESIS_TOOL_ALTERA_QUARTUS2,
+ SYNTHESIS_TOOL_LATTICE_LSE,
+ SYNTHESIS_TOOL_SYNOPSIS,
+ SYNTHESIS_TOOL_XILINX_XST,
+ SYNTHESIS_TOOL_XILINX_VIVADO
+ );
+
+ -- List of known device families
+ -- ---------------------------------------------------------------------------
+ type T_DEVICE_FAMILY is (
+ DEVICE_FAMILY_UNKNOWN,
+ -- Altera
+ DEVICE_FAMILY_ARRIA,
+ DEVICE_FAMILY_CYCLONE,
+ DEVICE_FAMILY_STRATIX,
+ -- Lattice
+ DEVICE_FAMILY_ICE,
+ DEVICE_FAMILY_MACHXO,
+ DEVICE_FAMILY_ECP,
+ -- Xilinx
+ DEVICE_FAMILY_SPARTAN,
+ DEVICE_FAMILY_ZYNQ,
+ DEVICE_FAMILY_ARTIX,
+ DEVICE_FAMILY_KINTEX,
+ DEVICE_FAMILY_VIRTEX
+ );
+
+ type T_DEVICE_SERIES is (
+ DEVICE_SERIES_UNKNOWN,
+ -- Xilinx FPGA series
+ DEVICE_SERIES_7_SERIES,
+ DEVICE_SERIES_ULTRASCALE,
+ DEVICE_SERIES_ULTRASCALE_PLUS
+ );
+
+ -- List of known devices
+ -- ---------------------------------------------------------------------------
+ type T_DEVICE is (
+ DEVICE_UNKNOWN,
+ -- Altera
+ DEVICE_MAX2, DEVICE_MAX10, -- Altera.Max
+ DEVICE_ARRIA1, DEVICE_ARRIA2, DEVICE_ARRIA5, DEVICE_ARRIA10, -- Altera.Arria
+ DEVICE_CYCLONE1, DEVICE_CYCLONE2, DEVICE_CYCLONE3, DEVICE_CYCLONE4, -- Altera.Cyclone
+ DEVICE_CYCLONE5, --
+ DEVICE_STRATIX1, DEVICE_STRATIX2, DEVICE_STRATIX3, DEVICE_STRATIX4, -- Altera.Stratix
+ DEVICE_STRATIX5, DEVICE_STRATIX10, --
+ -- Lattice
+ DEVICE_ICE40, DEVICE_ICE65, DEVICE_ICE5, -- Lattice.iCE
+ DEVICE_MACHXO, DEVICE_MACHXO2, -- Lattice.MachXO
+ DEVICE_ECP3, DEVICE_ECP4, DEVICE_ECP5, -- Lattice.ECP
+ -- Xilinx
+ DEVICE_SPARTAN3, DEVICE_SPARTAN6, -- Xilinx.Spartan
+ DEVICE_ZYNQ7, DEVICE_ZYNQ_ULTRA_PLUS, -- Xilinx.Zynq
+ DEVICE_ARTIX7, -- Xilinx.Artix
+ DEVICE_KINTEX7, DEVICE_KINTEX_ULTRA, DEVICE_KINTEX_ULTRA_PLUS, -- Xilinx.Kintex
+ DEVICE_VIRTEX5, DEVICE_VIRTEX6, DEVICE_VIRTEX7, -- Xilinx.Virtex
+ DEVICE_VIRTEX_ULTRA, DEVICE_VIRTEX_ULTRA_PLUS --
+ );
+
+ -- List of known device subtypes
+ -- ---------------------------------------------------------------------------
+ type T_DEVICE_SUBTYPE is (
+ DEVICE_SUBTYPE_NONE,
+ -- Altera
+ DEVICE_SUBTYPE_E,
+ DEVICE_SUBTYPE_GS,
+ DEVICE_SUBTYPE_GX,
+ DEVICE_SUBTYPE_GT,
+ -- Lattice
+ DEVICE_SUBTYPE_U,
+ DEVICE_SUBTYPE_UM,
+ -- Xilinx
+ DEVICE_SUBTYPE_X,
+ DEVICE_SUBTYPE_T,
+ DEVICE_SUBTYPE_XT,
+ DEVICE_SUBTYPE_HT,
+ DEVICE_SUBTYPE_LX,
+ DEVICE_SUBTYPE_SXT,
+ DEVICE_SUBTYPE_LXT,
+ DEVICE_SUBTYPE_TXT,
+ DEVICE_SUBTYPE_FXT,
+ DEVICE_SUBTYPE_CXT,
+ DEVICE_SUBTYPE_HXT
+ );
+
+ -- List of known transceiver (sub-)types
+ -- ---------------------------------------------------------------------------
+ type T_TRANSCEIVER is (
+ TRANSCEIVER_NONE,
+ -- TODO: add more? Altera transceivers
+ -- Altera transceivers
+ TRANSCEIVER_GXB, -- Altera GXB transceiver
+ --Lattice transceivers
+ TRANSCEIVER_MGT, -- Lattice transceiver
+ -- Xilinx transceivers
+ TRANSCEIVER_GTP_DUAL, TRANSCEIVER_GTPE1, TRANSCEIVER_GTPE2, -- Xilinx GTP transceivers
+ TRANSCEIVER_GTX, TRANSCEIVER_GTXE1, TRANSCEIVER_GTXE2, -- Xilinx GTX transceivers
+ TRANSCEIVER_GTH, TRANSCEIVER_GTHE1, TRANSCEIVER_GTHE2, -- Xilinx GTH transceivers
+ TRANSCEIVER_GTZ, -- Xilinx GTZ transceivers
+ TRANSCEIVER_GTY -- Xilinx GTY transceivers
+ );
+
+ -- Properties of an FPGA architecture
+ -- ===========================================================================
+ type T_DEVICE_INFO is record
+ Vendor : T_VENDOR;
+ Device : T_DEVICE;
+ DevFamily : T_DEVICE_FAMILY;
+ DevNumber : natural;
+ DevSubType : T_DEVICE_SUBTYPE;
+ DevSeries : T_DEVICE_SERIES;
+
+ TransceiverType : T_TRANSCEIVER;
+ LUT_FanIn : positive;
+ end record;
+
+ -- Functions extracting board and PCB properties from "MY_BOARD"
+ -- which is declared in package "my_config".
+ -- ===========================================================================
+ function BOARD(BoardConfig : string := C_BOARD_STRING_EMPTY) return NATURAL;
+ function BOARD_INFO(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return T_BOARD_INFO;
+ function BOARD_NAME(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING;
+ function BOARD_DEVICE(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING;
+ function BOARD_UART_BAUDRATE(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING;
+
+ -- Functions extracting device and architecture properties from "MY_DEVICE"
+ -- which is declared in package "my_config".
+ -- ===========================================================================
+ function VENDOR(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_VENDOR;
+ function SYNTHESIS_TOOL(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_SYNTHESIS_TOOL;
+ function DEVICE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE;
+ function DEVICE_FAMILY(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_FAMILY;
+ function DEVICE_NUMBER(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural;
+ function DEVICE_SUBTYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_SUBTYPE;
+ function DEVICE_SERIES(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_SERIES;
+
+ function TRANSCEIVER_TYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_TRANSCEIVER;
+ function LUT_FANIN(DeviceString : string := C_DEVICE_STRING_EMPTY) return positive;
+
+ function DEVICE_INFO(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_INFO;
+
+ -- force FSM to predefined encoding in debug mode
+ function getFSMEncoding_gray(debug : BOOLEAN) return STRING;
+end package;
+
+
+package body config is
+ -- inlined function from PoC.utils, to break dependency
+ -- ===========================================================================
+ function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING is begin
+ if cond then return value1; else return value2; end if;
+ end function;
+
+ -- chr_is* function
+ function chr_isDigit(chr : CHARACTER) return boolean is
+ begin
+ return ((CHARACTER'pos('0') <= CHARACTER'pos(chr)) and (CHARACTER'pos(chr) <= CHARACTER'pos('9')));
+ end function;
+
+ function chr_isAlpha(chr : character) return boolean is
+ begin
+ return (((CHARACTER'pos('a') <= CHARACTER'pos(chr)) and (CHARACTER'pos(chr) <= CHARACTER'pos('z'))) or
+ ((CHARACTER'pos('A') <= CHARACTER'pos(chr)) and (CHARACTER'pos(chr) <= CHARACTER'pos('Z'))));
+ end function;
+
+ function str_length(str : STRING) return NATURAL is
+ begin
+ for i in str'range loop
+ if (str(i) = C_POC_NUL) then
+ return i - str'low;
+ end if;
+ end loop;
+ return str'length;
+ end function;
+
+ function str_trim(str : STRING) return STRING is
+ begin
+ for i in str'range loop
+ if (str(i) = C_POC_NUL) then
+ return str(str'low to i-1);
+ end if;
+ end loop;
+ return str;
+ end function;
+
+ function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN is
+ constant len : NATURAL := imin(str1'length, str2'length);
+ variable chr1 : CHARACTER;
+ variable chr2 : CHARACTER;
+ begin
+ -- if both strings are empty
+ if ((str1'length = 0 ) and (str2'length = 0)) then return TRUE; end if;
+ -- compare char by char
+ for i in 0 to len-1 loop
+ chr1 := str1(str1'low + i);
+ chr2 := str2(str2'low + i);
+ if (CHARACTER'pos('A') <= CHARACTER'pos(chr1)) and (CHARACTER'pos(chr1) <= CHARACTER'pos('Z')) then
+ chr1 := CHARACTER'val(CHARACTER'pos(chr1) - CHARACTER'pos('A') + CHARACTER'pos('a'));
+ end if;
+ if (CHARACTER'pos('A') <= CHARACTER'pos(chr2)) and (CHARACTER'pos(chr2) <= CHARACTER'pos('Z')) then
+ chr2 := CHARACTER'val(CHARACTER'pos(chr2) - CHARACTER'pos('A') + CHARACTER'pos('a'));
+ end if;
+ if (chr1 /= chr2) then
+ return FALSE;
+ elsif ((chr1 = C_POC_NUL) xor (chr2 = C_POC_NUL)) then
+ return FALSE;
+ elsif ((chr1 = C_POC_NUL) and (chr2 = C_POC_NUL)) then
+ return TRUE;
+ end if;
+ end loop;
+ -- check special cases,
+ if ((str1'length = len) and (str2'length = len)) then -- both strings are fully consumed and equal
+ return TRUE;
+ elsif (str1'length > len) then
+ return (str1(str1'low + len) = C_POC_NUL); -- str1 is longer, but str_length equals len
+ else
+ return (str2(str2'low + len) = C_POC_NUL); -- str2 is longer, but str_length equals len
+ end if;
+ end function;
+
+ function str_find(str : STRING; pattern : STRING; start : NATURAL := 0) return BOOLEAN is
+ begin
+ for i in imax(str'low, start) to (str'high - pattern'length + 1) loop
+ exit when (str(i) = C_POC_NUL);
+ if (str(i to i + pattern'length - 1) = pattern) then
+ return TRUE;
+ end if;
+ end loop;
+ return FALSE;
+ end function;
+
+ -- private functions required by board description
+ -- ModelSim requires that this functions is defined before it is used below.
+ -- ===========================================================================
+ function getLocalDeviceString(DeviceString : STRING) return STRING is
+ constant ConstNUL : STRING(1 to 1) := (others => C_POC_NUL);
+ constant MY_DEVICE_STR : STRING := BOARD_DEVICE;
+ variable Result : STRING(1 to T_DEVICE_STRING'length);
+ begin
+ Result := (others => C_POC_NUL);
+ -- report DeviceString for debugging
+ if (POC_VERBOSE = TRUE) then
+ report "getLocalDeviceString: DeviceString='" & str_trim(DeviceString) & "' MY_DEVICE='" & str_trim(MY_DEVICE) & "' MY_DEVICE_STR='" & str_trim(MY_DEVICE_STR) & "'" severity NOTE;
+ end if;
+ -- if DeviceString is populated
+ if ((str_length(DeviceString) /= 0) and (str_imatch(DeviceString, "None") = FALSE)) then
+ Result(1 to imin(T_DEVICE_STRING'length, imax(1, DeviceString'length))) := ite((DeviceString'length > 0), DeviceString(1 to imin(T_DEVICE_STRING'length, DeviceString'length)), ConstNUL);
+ -- if MY_DEVICE is set, prefer it
+ elsif ((str_length(MY_DEVICE) /= 0) and (str_imatch(MY_DEVICE, "None") = FALSE)) then
+ Result(1 to imin(T_DEVICE_STRING'length, imax(1, MY_DEVICE'length))) := ite((MY_DEVICE'length > 0), MY_DEVICE(1 to imin(T_DEVICE_STRING'length, MY_DEVICE'length)), ConstNUL);
+ -- otherwise use MY_BOARD
+ else
+ Result(1 to imin(T_DEVICE_STRING'length, imax(1, MY_DEVICE_STR'length))) := ite((MY_DEVICE_STR'length > 0), MY_DEVICE_STR(1 to imin(T_DEVICE_STRING'length, MY_DEVICE_STR'length)), ConstNUL);
+ end if;
+ return Result;
+ end function;
+
+ function extractFirstNumber(str : STRING) return NATURAL is
+ variable low : integer;
+ variable high : integer;
+ variable Result : NATURAL;
+ variable Digit : INTEGER;
+ begin
+ low := -1;
+ high := -1;
+ for i in str'low to str'high loop
+ if chr_isDigit(str(i)) then
+ low := i;
+ exit;
+ end if;
+ end loop;
+ -- abort if no digit can be found
+ if (low = -1) then return 0; end if;
+
+ for i in (low + 1) to str'high loop
+ if chr_isAlpha(str(i)) then
+ high := i - 1;
+ exit;
+ end if;
+ end loop;
+
+ if (high = -1) then return 0; end if;
+ -- return INTEGER'value(str(low to high)); -- 'value(...) is not supported by Vivado Synth 2014.1
+
+ -- convert substring to a number
+ for i in low to high loop
+ if (chr_isDigit(str(i)) = FALSE) then
+ return 0;
+ end if;
+ Result := (Result * 10) + (character'pos(str(i)) - character'pos('0'));
+ end loop;
+ return Result;
+ end function;
+
+ -- Public functions
+ -- ===========================================================================
+ -- TODO: comment
+ function BOARD(BoardConfig : string := C_BOARD_STRING_EMPTY) return NATURAL is
+ constant MY_BRD : T_BOARD_CONFIG_STRING := ite((BoardConfig /= C_BOARD_STRING_EMPTY), conf(BoardConfig), conf(MY_BOARD));
+ constant BOARD_NAME : STRING := str_trim(MY_BRD);
+ begin
+ if (POC_VERBOSE = TRUE) then report "PoC configuration: Used board is '" & BOARD_NAME & "'" severity NOTE; end if;
+ for i in C_BOARD_INFO_LIST'range loop
+ if str_imatch(BOARD_NAME, C_BOARD_INFO_LIST(i).BoardName) then
+ return i;
+ end if;
+ end loop;
+
+ report "Unknown board name in MY_BOARD = " & MY_BRD & "." severity failure;
+ return C_BOARD_INFO_LIST'high;
+ end function;
+
+ function BOARD_INFO(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return T_BOARD_INFO is
+ constant BRD : NATURAL := BOARD(BoardConfig);
+ begin
+ return C_BOARD_INFO_LIST(BRD);
+ end function;
+
+ -- TODO: comment
+ function BOARD_NAME(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING is
+ constant BRD : NATURAL := BOARD(BoardConfig);
+ begin
+ return str_trim(C_BOARD_INFO_LIST(BRD).BoardName);
+ end function;
+
+ -- TODO: comment
+ function BOARD_DEVICE(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING is
+ constant BRD : NATURAL := BOARD(BoardConfig);
+ begin
+ return str_trim(C_BOARD_INFO_LIST(BRD).FPGADevice);
+ end function;
+
+ function BOARD_UART_BAUDRATE(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING is
+ constant BRD : NATURAL := BOARD(BoardConfig);
+ begin
+ return str_trim(C_BOARD_INFO_LIST(BRD).UART.BaudRate);
+ end function;
+
+ -- purpose: extract vendor from MY_DEVICE
+ function VENDOR(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_VENDOR is
+ constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
+ constant VEN_STR2 : string(1 to 2) := MY_DEV(1 to 2);
+ constant VEN_STR3 : string(1 to 3) := MY_DEV(1 to 3);
+ begin
+ case VEN_STR2 is
+ when "EP" => return VENDOR_ALTERA;
+ when "XC" => return VENDOR_XILINX;
+ when others => null;
+ end case;
+ case VEN_STR3 is
+ when "iCE" => return VENDOR_LATTICE; -- iCE devices
+ when "LCM" => return VENDOR_LATTICE; -- MachXO device
+ when "LFE" => return VENDOR_LATTICE; -- ECP devices
+ when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure;
+ -- return statement is explicitly missing otherwise XST won't stop
+ end case;
+ end function;
+
+ function SYNTHESIS_TOOL(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_SYNTHESIS_TOOL is
+ constant VEN : T_VENDOR := VENDOR(DeviceString);
+ begin
+ case VEN is
+ when VENDOR_ALTERA =>
+ return SYNTHESIS_TOOL_ALTERA_QUARTUS2;
+ when VENDOR_LATTICE =>
+ return SYNTHESIS_TOOL_LATTICE_LSE;
+ --return SYNTHESIS_TOOL_SYNOPSIS;
+ when VENDOR_XILINX =>
+ if (1 fs /= 1 us) then
+ return SYNTHESIS_TOOL_XILINX_XST;
+ else
+ return SYNTHESIS_TOOL_XILINX_VIVADO;
+ end if;
+ when others =>
+ return SYNTHESIS_TOOL_UNKNOWN;
+ end case;
+ end function;
+
+ -- purpose: extract device from MY_DEVICE
+ function DEVICE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE is
+ constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
+ constant VEN : T_VENDOR := VENDOR(DeviceString);
+ constant DEV_STR : string(3 to 4) := MY_DEV(3 to 4);
+ begin
+ case VEN is
+ when VENDOR_ALTERA =>
+ case DEV_STR is
+ when "1C" => return DEVICE_CYCLONE1;
+ when "2C" => return DEVICE_CYCLONE2;
+ when "3C" => return DEVICE_CYCLONE3;
+ when "1S" => return DEVICE_STRATIX1;
+ when "2S" => return DEVICE_STRATIX2;
+ when "4S" => return DEVICE_STRATIX4;
+ when "5S" => return DEVICE_STRATIX5;
+ when others => report "Unknown Altera device in MY_DEVICE = '" & MY_DEV & "'" severity failure;
+ end case;
+
+ when VENDOR_LATTICE =>
+ if (MY_DEV(1 to 6) = "LCMX02") then return DEVICE_MACHXO2;
+ elsif (MY_DEV(1 to 5) = "LCMX0") then return DEVICE_MACHXO;
+ elsif (MY_DEV(1 to 5) = "iCE40") then return DEVICE_ICE40;
+ elsif (MY_DEV(1 to 5) = "iCE65") then return DEVICE_ICE65;
+ elsif (MY_DEV(1 to 4) = "iCE5") then return DEVICE_ICE5;
+ elsif (MY_DEV(1 to 4) = "LFE3") then return DEVICE_ECP3;
+ elsif (MY_DEV(1 to 4) = "LFE4") then return DEVICE_ECP4;
+ elsif (MY_DEV(1 to 4) = "LFE5") then return DEVICE_ECP5;
+ else report "Unknown Lattice device in MY_DEVICE = '" & MY_DEV & "'" severity failure;
+ end if;
+
+ when VENDOR_XILINX =>
+ case DEV_STR is
+ when "7A" => return DEVICE_ARTIX7;
+ when "7K" => return DEVICE_KINTEX7;
+ when "KU" => return DEVICE_KINTEX_ULTRA;
+ when "3S" => return DEVICE_SPARTAN3;
+ when "6S" => return DEVICE_SPARTAN6;
+ when "5V" => return DEVICE_VIRTEX5;
+ when "6V" => return DEVICE_VIRTEX6;
+ when "7V" => return DEVICE_VIRTEX7;
+ when "VU" => return DEVICE_VIRTEX_ULTRA;
+ when "7Z" => return DEVICE_ZYNQ7;
+ when others => report "Unknown Xilinx device in MY_DEVICE = '" & MY_DEV & "'" severity failure;
+ end case;
+
+ when others => report "Unknown vendor in MY_DEVICE = " & MY_DEV & "." severity failure;
+ -- return statement is explicitly missing otherwise XST won't stop
+ end case;
+ end function;
+
+ -- purpose: extract device from MY_DEVICE
+ function DEVICE_FAMILY(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_FAMILY is
+ constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
+ constant VEN : T_VENDOR := VENDOR(DeviceString);
+ constant FAM_CHAR : character := MY_DEV(4);
+ begin
+ case VEN is
+ when VENDOR_ALTERA =>
+ case FAM_CHAR is
+ when 'C' => return DEVICE_FAMILY_CYCLONE;
+ when 'S' => return DEVICE_FAMILY_STRATIX;
+ when others => report "Unknown Altera device family in MY_DEVICE = '" & MY_DEV & "'" severity failure;
+ end case;
+
+ when VENDOR_LATTICE =>
+ case FAM_CHAR is
+ --when 'M' => return DEVICE_FAMILY_MACHXO;
+ when 'E' => return DEVICE_FAMILY_ECP;
+ when others => report "Unknown Lattice device family in MY_DEVICE = '" & MY_DEV & "'" severity failure;
+ end case;
+
+ when VENDOR_XILINX =>
+ case FAM_CHAR is
+ when 'A' => return DEVICE_FAMILY_ARTIX;
+ when 'K' => return DEVICE_FAMILY_KINTEX;
+ when 'S' => return DEVICE_FAMILY_SPARTAN;
+ when 'V' => return DEVICE_FAMILY_VIRTEX;
+ when 'Z' => return DEVICE_FAMILY_ZYNQ;
+ when others => report "Unknown Xilinx device family in MY_DEVICE = '" & MY_DEV & "'" severity failure;
+ end case;
+
+ when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure;
+ -- return statement is explicitly missing otherwise XST won't stop
+ end case;
+ end function;
+
+ -- some devices share some common features: e.g. XADC, BlockRAM, ...
+ function DEVICE_SERIES(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_SERIES is
+ constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
+ constant DEV : T_DEVICE := DEVICE(DeviceString);
+ begin
+ case DEV is
+ -- all Xilinx ****7 devices
+ when DEVICE_ARTIX7 | DEVICE_KINTEX7 | DEVICE_VIRTEX7 | DEVICE_ZYNQ7 =>
+ return DEVICE_SERIES_7_SERIES;
+ -- all Xilinx ****UltraScale devices
+ when DEVICE_KINTEX_ULTRA | DEVICE_VIRTEX_ULTRA =>
+ return DEVICE_SERIES_ULTRASCALE;
+ -- all Xilinx ****UltraScale+ devices
+ when DEVICE_KINTEX_ULTRA_PLUS | DEVICE_VIRTEX_ULTRA_PLUS | DEVICE_ZYNQ_ULTRA_PLUS =>
+ return DEVICE_SERIES_ULTRASCALE_PLUS;
+ when others =>
+ return DEVICE_SERIES_UNKNOWN;
+ end case;
+ end function;
+
+ function DEVICE_NUMBER(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural is
+ constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
+ constant VEN : T_VENDOR := VENDOR(DeviceString);
+ begin
+ case VEN is
+ when VENDOR_ALTERA => return extractFirstNumber(MY_DEV(5 to MY_DEV'high));
+ when VENDOR_LATTICE => return extractFirstNumber(MY_DEV(6 to MY_DEV'high));
+ when VENDOR_XILINX => return extractFirstNumber(MY_DEV(5 to MY_DEV'high));
+ when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure;
+ -- return statement is explicitly missing otherwise XST won't stop
+ end case;
+ end function;
+
+ function DEVICE_SUBTYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return t_device_subtype is
+ constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
+ constant DEV : T_DEVICE := DEVICE(MY_DEV);
+ constant DEV_SUB_STR : string(1 to 2) := MY_DEV(5 to 6); -- work around for GHDL
+ begin
+ case DEV is
+ -- TODO: extract Arria GX subtype
+ when DEVICE_ARRIA1 =>
+ report "TODO: parse Arria device subtype." severity failure;
+ return DEVICE_SUBTYPE_NONE;
+ -- TODO: extract ArriaII GX,GZ subtype
+ when DEVICE_ARRIA2 =>
+ report "TODO: parse ArriaII device subtype." severity failure;
+ return DEVICE_SUBTYPE_NONE;
+ -- TODO: extract ArriaV GX, GT, SX, GZ subtype
+ when DEVICE_ARRIA5 =>
+ report "TODO: parse ArriaV device subtype." severity failure;
+ return DEVICE_SUBTYPE_NONE;
+ -- TODO: extract Arria10 GX, GT, SX subtype
+ when DEVICE_ARRIA10 =>
+ report "TODO: parse Arria10 device subtype." severity failure;
+ return DEVICE_SUBTYPE_NONE;
+ -- Altera Cyclon I, II, III, IV, V devices have no subtype
+ when DEVICE_CYCLONE1 | DEVICE_CYCLONE2 | DEVICE_CYCLONE3 | DEVICE_CYCLONE4 |
+ DEVICE_CYCLONE5 => return DEVICE_SUBTYPE_NONE;
+
+ when DEVICE_STRATIX2 =>
+ if chr_isDigit(DEV_SUB_STR(1)) then return DEVICE_SUBTYPE_NONE;
+ elsif (DEV_SUB_STR = "GX") then return DEVICE_SUBTYPE_GX;
+ else report "Unknown Stratix II subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
+ end if;
+
+ when DEVICE_STRATIX4 =>
+ if (DEV_SUB_STR(1) = 'E') then return DEVICE_SUBTYPE_E;
+ elsif (DEV_SUB_STR = "GX") then return DEVICE_SUBTYPE_GX;
+-- elsif (DEV_SUB_STR = "GT") then return DEVICE_SUBTYPE_GT;
+ else report "Unknown Stratix IV subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
+ end if;
+
+ -- TODO: extract StratixV subtype
+ when DEVICE_STRATIX5 =>
+ report "TODO: parse Stratix V device subtype." severity failure;
+ return DEVICE_SUBTYPE_NONE;
+
+ when DEVICE_ECP5 =>
+ if (DEV_SUB_STR(1) = 'U') then return DEVICE_SUBTYPE_U;
+ elsif (DEV_SUB_STR = "UM") then return DEVICE_SUBTYPE_UM;
+ else report "Unknown Lattice ECP5 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
+ end if;
+
+ when DEVICE_SPARTAN3 =>
+ report "TODO: parse Spartan3 / Spartan3E / Spartan3AN device subtype." severity failure;
+ return DEVICE_SUBTYPE_NONE;
+
+ when DEVICE_SPARTAN6 =>
+ if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX;
+ elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT;
+ else report "Unknown Virtex-5 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
+ end if;
+
+ when DEVICE_VIRTEX5 =>
+ if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX;
+ elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT;
+ elsif ((DEV_SUB_STR = "SX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_SXT;
+ elsif ((DEV_SUB_STR = "TX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_TXT;
+ elsif ((DEV_SUB_STR = "FX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_FXT;
+ else report "Unknown Virtex-5 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
+ end if;
+
+ when DEVICE_VIRTEX6 =>
+ if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX;
+ elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT;
+ elsif ((DEV_SUB_STR = "SX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_SXT;
+ elsif ((DEV_SUB_STR = "CX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_CXT;
+ elsif ((DEV_SUB_STR = "HX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_HXT;
+ else report "Unknown Virtex-6 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
+ end if;
+
+ when DEVICE_ARTIX7 =>
+ if ( ( str_find(MY_DEV(5 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T;
+ else report "Unknown Artix-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
+ end if;
+
+ when DEVICE_KINTEX7 =>
+ if ( ( str_find(MY_DEV(5 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T;
+ else report "Unknown Kintex-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
+ end if;
+
+ when DEVICE_KINTEX_ULTRA => return DEVICE_SUBTYPE_NONE;
+ when DEVICE_KINTEX_ULTRA_PLUS => return DEVICE_SUBTYPE_NONE;
+
+ when DEVICE_VIRTEX7 =>
+ if ( ( str_find(MY_DEV(5 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T;
+ elsif ((DEV_SUB_STR(1) = 'X') and ( str_find(MY_DEV(6 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_XT;
+ elsif ((DEV_SUB_STR(1) = 'H') and ( str_find(MY_DEV(6 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_HT;
+ else report "Unknown Virtex-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
+ end if;
+
+ when DEVICE_VIRTEX_ULTRA => return DEVICE_SUBTYPE_NONE;
+ when DEVICE_VIRTEX_ULTRA_PLUS => return DEVICE_SUBTYPE_NONE;
+
+ when DEVICE_ZYNQ7 => return DEVICE_SUBTYPE_NONE;
+ when DEVICE_ZYNQ_ULTRA_PLUS => return DEVICE_SUBTYPE_NONE;
+
+ when others => report "Device sub-type is unknown for the given device." severity failure;
+ -- return statement is explicitly missing otherwise XST won't stop
+ end case;
+
+ end function;
+
+ function LUT_FANIN(DeviceString : string := C_DEVICE_STRING_EMPTY) return positive is
+ constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
+ constant DEV : T_DEVICE := DEVICE(DeviceString);
+ constant SERIES : T_DEVICE_SERIES := DEVICE_SERIES(DeviceString);
+ begin
+ case SERIES is
+ when DEVICE_SERIES_7_SERIES | DEVICE_SERIES_ULTRASCALE |
+ DEVICE_SERIES_ULTRASCALE_PLUS => return 6;
+ when others => null;
+ end case;
+ case DEV is
+ when DEVICE_CYCLONE1 | DEVICE_CYCLONE2 | DEVICE_CYCLONE3 => return 4;
+ when DEVICE_STRATIX1 | DEVICE_STRATIX2 => return 4;
+ when DEVICE_STRATIX4 | DEVICE_STRATIX5 => return 6;
+
+ when DEVICE_ECP5 => return 4;
+
+ when DEVICE_SPARTAN3 => return 4;
+ when DEVICE_SPARTAN6 => return 6;
+ when DEVICE_VIRTEX5 | DEVICE_VIRTEX6 => return 6;
+
+ when others => report "LUT fan-in is unknown for the given device." severity failure;
+ -- return statement is explicitly missing otherwise XST won't stop
+ end case;
+ end function;
+
+ function TRANSCEIVER_TYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_TRANSCEIVER is
+ constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
+ constant DEV : T_DEVICE := DEVICE(DeviceString);
+ constant DEV_NUM : natural := DEVICE_NUMBER(DeviceString);
+ constant DEV_SUB : t_device_subtype := DEVICE_SUBTYPE(DeviceString);
+ begin
+ case DEV is
+ when DEVICE_MAX2 | DEVICE_MAX10 => return TRANSCEIVER_NONE; -- Altera MAX II, 10 devices have no transceivers
+ when DEVICE_CYCLONE1 | DEVICE_CYCLONE2 | DEVICE_CYCLONE3 => return TRANSCEIVER_NONE; -- Altera Cyclon I, II, III devices have no transceivers
+
+ when DEVICE_STRATIX2 => return TRANSCEIVER_GXB;
+ when DEVICE_STRATIX4 => return TRANSCEIVER_GXB;
+ --when DEVICE_STRATIX5 => return TRANSCEIVER_GXB;
+
+ when DEVICE_ECP5 => return TRANSCEIVER_MGT;
+
+ when DEVICE_SPARTAN3 => return TRANSCEIVER_NONE; -- Xilinx Spartan3 devices have no transceivers
+ when DEVICE_SPARTAN6 =>
+ case DEV_SUB is
+ when DEVICE_SUBTYPE_LX => return TRANSCEIVER_NONE;
+ when DEVICE_SUBTYPE_LXT => return TRANSCEIVER_GTPE1;
+ when others => report "Unknown Spartan-6 subtype: " & t_device_subtype'image(DEV_SUB) severity failure;
+ end case;
+
+ when DEVICE_VIRTEX5 =>
+ case DEV_SUB is
+ when DEVICE_SUBTYPE_LX => return TRANSCEIVER_NONE;
+ when DEVICE_SUBTYPE_SXT => return TRANSCEIVER_GTP_DUAL;
+ when DEVICE_SUBTYPE_LXT => return TRANSCEIVER_GTP_DUAL;
+ when DEVICE_SUBTYPE_TXT => return TRANSCEIVER_GTX;
+ when DEVICE_SUBTYPE_FXT => return TRANSCEIVER_GTX;
+ when others => report "Unknown Virtex-5 subtype: " & t_device_subtype'image(DEV_SUB) severity failure;
+ end case;
+
+ when DEVICE_VIRTEX6 =>
+ case DEV_SUB is
+ when DEVICE_SUBTYPE_LX => return TRANSCEIVER_NONE;
+ when DEVICE_SUBTYPE_SXT => return TRANSCEIVER_GTXE1;
+ when DEVICE_SUBTYPE_LXT => return TRANSCEIVER_GTXE1;
+ when DEVICE_SUBTYPE_HXT => return TRANSCEIVER_GTXE1;
+ when others => report "Unknown Virtex-6 subtype: " & t_device_subtype'image(DEV_SUB) severity failure;
+ end case;
+
+ when DEVICE_ARTIX7 => return TRANSCEIVER_GTPE2;
+ when DEVICE_KINTEX7 => return TRANSCEIVER_GTXE2;
+ when DEVICE_VIRTEX7 =>
+ case DEV_SUB is
+ when DEVICE_SUBTYPE_T => return TRANSCEIVER_GTXE2;
+ when DEVICE_SUBTYPE_XT =>
+ if (DEV_NUM = 485) then return TRANSCEIVER_GTXE2;
+ else return TRANSCEIVER_GTHE2;
+ end if;
+ when DEVICE_SUBTYPE_HT => return TRANSCEIVER_GTHE2;
+ when others => report "Unknown Virtex-7 subtype: " & t_device_subtype'image(DEV_SUB) severity failure;
+ end case;
+ when DEVICE_ZYNQ7 =>
+ case DEV_NUM is
+ when 10 | 20 => return TRANSCEIVER_NONE;
+ when 15 => return TRANSCEIVER_GTPE2;
+ when others => return TRANSCEIVER_GTXE2;
+ end case;
+
+ when others => report "Unknown device." severity failure;
+ -- return statement is explicitly missing otherwise XST won't stop
+ end case;
+ end function;
+
+ -- purpose: extract architecture properties from DEVICE
+ function DEVICE_INFO(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_INFO is
+ variable Result : T_DEVICE_INFO;
+ begin
+ Result.Vendor := VENDOR(DeviceString);
+ Result.Device := DEVICE(DeviceString);
+ Result.DevFamily := DEVICE_FAMILY(DeviceString);
+ Result.DevNumber := DEVICE_NUMBER(DeviceString);
+ Result.DevSubType := DEVICE_SUBTYPE(DeviceString);
+ Result.DevSeries := DEVICE_SERIES(DeviceString);
+ Result.TransceiverType := TRANSCEIVER_TYPE(DeviceString);
+ Result.LUT_FanIn := LUT_FANIN(DeviceString);
+
+ return Result;
+ end function;
+
+ -- force FSM to predefined encoding in debug mode
+ function getFSMEncoding_gray(debug : BOOLEAN) return STRING is
+ begin
+ if (debug = true) then
+ return "gray";
+ else
+ case VENDOR is
+ when VENDOR_ALTERA => return "default";
+ --when VENDOR_LATTICE => return "default";
+ when VENDOR_XILINX => return "auto";
+ when others => report "Unknown vendor." severity failure;
+ -- return statement is explicitly missing otherwise XST won't stop
+ end case;
+ end if;
+ end function;
+end package body;
diff --git a/testsuite/gna/bug037/my_config_ML505.vhdl b/testsuite/gna/bug037/my_config_ML505.vhdl new file mode 100644 index 000000000..cc132875d --- /dev/null +++ b/testsuite/gna/bug037/my_config_ML505.vhdl @@ -0,0 +1,45 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+--
+-- =============================================================================
+-- Authors: Thomas B. Preusser
+-- Martin Zabel
+-- Patrick Lehmann
+--
+-- Package: Project specific configuration.
+--
+-- Description:
+-- ------------------------------------
+-- This file was created from template <PoCRoot>/src/common/my_config.template.vhdl.
+--
+--
+-- License:
+-- =============================================================================
+-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
+-- Chair for VLSI-Design, Diagnostics and Architecture
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+
+library PoC;
+
+
+package my_config is
+ -- Change these lines to setup configuration.
+ constant MY_BOARD : string := "ML505"; -- ML505 - Xilinx Virtex 5 reference design board: XC5VLX50T
+ constant MY_DEVICE : string := "None"; -- infer from MY_BOARD
+
+ -- For internal use only
+ constant MY_VERBOSE : boolean := FALSE;
+end package;
diff --git a/testsuite/gna/bug037/my_project.vhdl b/testsuite/gna/bug037/my_project.vhdl new file mode 100644 index 000000000..948f0ca1e --- /dev/null +++ b/testsuite/gna/bug037/my_project.vhdl @@ -0,0 +1,39 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+--
+-- =============================================================================
+-- Authors: Patrick Lehmann
+--
+-- Package: Project specific configuration.
+--
+-- Description:
+-- ------------------------------------
+-- This file was created from template <PoCRoot>/src/common/my_project.template.vhdl.
+--
+-- License:
+-- =============================================================================
+-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
+-- Chair for VLSI-Design, Diagnostics and Architecture
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+
+library PoC;
+
+
+package my_project is
+ -- Change these lines to setup configuration.
+ constant MY_PROJECT_DIR : string := "D:/git/PoC-Examples/"; -- e.g. "d:/vhdl/myproject/", "/home/me/projects/myproject/"
+ constant MY_OPERATING_SYSTEM : string := "WINDOWS"; -- e.g. "WINDOWS", "LINUX"
+end;
diff --git a/testsuite/gna/bug037/physical.vhdl b/testsuite/gna/bug037/physical.vhdl new file mode 100644 index 000000000..26f60ab9c --- /dev/null +++ b/testsuite/gna/bug037/physical.vhdl @@ -0,0 +1,981 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+--
+-- ============================================================================
+-- Authors: Patrick Lehmann
+-- Martin Zabel
+--
+-- Package: This VHDL package declares new physical types and their
+-- conversion functions.
+--
+-- Description:
+-- ------------------------------------
+-- For detailed documentation see below.
+--
+-- NAMING CONVENTION:
+-- t - time
+-- p - period
+-- d - delay
+-- f - frequency
+-- br - baud rate
+-- vec - vector
+--
+-- ATTENTION:
+-- This package is not supported by Xilinx Synthese Tools prior to 14.7!
+--
+-- It was successfully tested with:
+-- - Xilinx Synthesis Tool (XST) 14.7 and Xilinx ISE Simulator (iSim) 14.7
+-- - Quartus II 13.1
+-- - QuestaSim 10.0d
+-- - GHDL 0.31
+--
+-- Tool chains with known issues:
+-- - Xilinx Vivado Synthesis 2014.4
+--
+-- Untested tool chains
+-- - Xilinx Vivado Simulator (xSim) 2014.4
+--
+-- License:
+-- ============================================================================
+-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
+-- Chair for VLSI-Design, Diagnostics and Architecture
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- ============================================================================
+
+library IEEE;
+use IEEE.math_real.all;
+
+library PoC;
+use PoC.config.all;
+use PoC.utils.all;
+use PoC.strings.all;
+
+
+package physical is
+
+ type FREQ is range 0 to INTEGER'high units
+ Hz;
+ kHz = 1000 Hz;
+ MHz = 1000 kHz;
+ GHz = 1000 MHz;
+ end units;
+
+ type BAUD is range 0 to INTEGER'high units
+ Bd;
+ kBd = 1000 Bd;
+ MBd = 1000 kBd;
+ GBd = 1000 MBd;
+ end units;
+
+ type MEMORY is range 0 to INTEGER'high units
+ Byte;
+ KiB = 1024 Byte;
+ MiB = 1024 KiB;
+ GiB = 1024 MiB;
+ end units;
+
+ -- vector data types
+ type T_TIMEVEC is array(NATURAL range <>) of TIME;
+ type T_FREQVEC is array(NATURAL range <>) of FREQ;
+ type T_BAUDVEC is array(NATURAL range <>) of BAUD;
+ type T_MEMVEC is array(NATURAL range <>) of MEMORY;
+
+ -- if true: TimingToCycles reports difference between expected and actual result
+ constant C_PHYSICAL_REPORT_TIMING_DEVIATION : BOOLEAN := TRUE;
+
+ -- conversion functions
+ function to_time(f : FREQ) return TIME;
+ function to_freq(p : TIME) return FREQ;
+ function to_freq(br : BAUD) return FREQ;
+ function to_baud(str : STRING) return BAUD;
+
+ -- if-then-else
+ function ite(cond : BOOLEAN; value1 : TIME; value2 : TIME) return TIME;
+ function ite(cond : BOOLEAN; value1 : FREQ; value2 : FREQ) return FREQ;
+ function ite(cond : BOOLEAN; value1 : BAUD; value2 : BAUD) return BAUD;
+ function ite(cond : BOOLEAN; value1 : MEMORY; value2 : MEMORY) return MEMORY;
+
+ -- min/ max for 2 arguments
+ function tmin(arg1 : TIME; arg2 : TIME) return TIME; -- Calculates: min(arg1, arg2) for times
+ function fmin(arg1 : FREQ; arg2 : FREQ) return FREQ; -- Calculates: min(arg1, arg2) for frequencies
+ function bmin(arg1 : BAUD; arg2 : BAUD) return BAUD; -- Calculates: min(arg1, arg2) for symbols per second
+ function mmin(arg1 : MEMORY; arg2 : MEMORY) return MEMORY; -- Calculates: min(arg1, arg2) for memory
+
+ function tmax(arg1 : TIME; arg2 : TIME) return TIME; -- Calculates: max(arg1, arg2) for times
+ function fmax(arg1 : FREQ; arg2 : FREQ) return FREQ; -- Calculates: max(arg1, arg2) for frequencies
+ function bmax(arg1 : BAUD; arg2 : BAUD) return BAUD; -- Calculates: max(arg1, arg2) for symbols per second
+ function mmax(arg1 : MEMORY; arg2 : MEMORY) return MEMORY; -- Calculates: max(arg1, arg2) for memory
+
+ -- min/max/sum as vector aggregation
+ function tmin(vec : T_TIMEVEC) return TIME; -- Calculates: min(vec) for a time vector
+ function fmin(vec : T_FREQVEC) return FREQ; -- Calculates: min(vec) for a frequency vector
+ function bmin(vec : T_BAUDVEC) return BAUD; -- Calculates: min(vec) for a baud vector
+ function mmin(vec : T_MEMVEC) return MEMORY; -- Calculates: min(vec) for a memory vector
+
+ function tmax(vec : T_TIMEVEC) return TIME; -- Calculates: max(vec) for a time vector
+ function fmax(vec : T_FREQVEC) return FREQ; -- Calculates: max(vec) for a frequency vector
+ function bmax(vec : T_BAUDVEC) return BAUD; -- Calculates: max(vec) for a baud vector
+ function mmax(vec : T_MEMVEC) return MEMORY; -- Calculates: max(vec) for a memory vector
+
+ function tsum(vec : T_TIMEVEC) return TIME; -- Calculates: sum(vec) for a time vector
+ function fsum(vec : T_FREQVEC) return FREQ; -- Calculates: sum(vec) for a frequency vector
+ function bsum(vec : T_BAUDVEC) return BAUD; -- Calculates: sum(vec) for a baud vector
+ function msum(vec : T_MEMVEC) return MEMORY; -- Calculates: sum(vec) for a memory vector
+
+ -- convert standard types (NATURAL, REAL) to time (TIME)
+ function fs2Time(t_fs : INTEGER) return TIME;
+ function ps2Time(t_ps : INTEGER) return TIME;
+ function ns2Time(t_ns : INTEGER) return TIME;
+ function us2Time(t_us : INTEGER) return TIME;
+ function ms2Time(t_ms : INTEGER) return TIME;
+ function sec2Time(t_sec : INTEGER) return TIME;
+
+ function fs2Time(t_fs : REAL) return TIME;
+ function ps2Time(t_ps : REAL) return TIME;
+ function ns2Time(t_ns : REAL) return TIME;
+ function us2Time(t_us : REAL) return TIME;
+ function ms2Time(t_ms : REAL) return TIME;
+ function sec2Time(t_sec : REAL) return TIME;
+
+ -- convert standard types (NATURAL, REAL) to period (TIME)
+ function Hz2Time(f_Hz : NATURAL) return TIME;
+ function kHz2Time(f_kHz : NATURAL) return TIME;
+ function MHz2Time(f_MHz : NATURAL) return TIME;
+ function GHz2Time(f_GHz : NATURAL) return TIME;
+
+ function Hz2Time(f_Hz : REAL) return TIME;
+ function kHz2Time(f_kHz : REAL) return TIME;
+ function MHz2Time(f_MHz : REAL) return TIME;
+ function GHz2Time(f_GHz : REAL) return TIME;
+
+ -- convert standard types (NATURAL, REAL) to frequency (FREQ)
+ function Hz2Freq(f_Hz : NATURAL) return FREQ;
+ function kHz2Freq(f_kHz : NATURAL) return FREQ;
+ function MHz2Freq(f_MHz : NATURAL) return FREQ;
+ function GHz2Freq(f_GHz : NATURAL) return FREQ;
+
+ function Hz2Freq(f_Hz : REAL) return FREQ;
+ function kHz2Freq(f_kHz : REAL) return FREQ;
+ function MHz2Freq(f_MHz : REAL) return FREQ;
+ function GHz2Freq(f_GHz : REAL) return FREQ;
+
+ -- convert physical types to standard type (REAL)
+ function to_real(t : TIME; scale : TIME) return REAL;
+ function to_real(f : FREQ; scale : FREQ) return REAL;
+ function to_real(br : BAUD; scale : BAUD) return REAL;
+ function to_real(mem : MEMORY; scale : MEMORY) return REAL;
+
+ -- convert physical types to standard type (INTEGER)
+ function to_int(t : TIME; scale : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
+ function to_int(f : FREQ; scale : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
+ function to_int(br : BAUD; scale : BAUD; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
+ function to_int(mem : MEMORY; scale : MEMORY; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return INTEGER;
+
+ -- calculate needed counter cycles to achieve a given 1. timing/delay and 2. frequency/period
+ function TimingToCycles(Timing : TIME; Clock_Period : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL;
+ function TimingToCycles(Timing : TIME; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL;
+
+ function CyclesToDelay(Cycles : NATURAL; Clock_Period : TIME) return TIME;
+ function CyclesToDelay(Cycles : NATURAL; Clock_Frequency : FREQ) return TIME;
+
+ -- convert and format physical types to STRING
+ function to_string(t : TIME; precision : NATURAL) return STRING;
+ function to_string(f : FREQ; precision : NATURAL) return STRING;
+ function to_string(br : BAUD; precision : NATURAL) return STRING;
+ function to_string(mem : MEMORY; precision : NATURAL) return STRING;
+end physical;
+
+
+package body physical is
+
+ -- iSim 14.7 does not support fs in simulation (fs values are converted to 0 ps)
+ function MinimalTimeResolutionInSimulation return TIME is
+ begin
+ if (1 fs > 0 sec) then return 1 fs;
+ elsif (1 ps > 0 sec) then return 1 ps;
+ elsif (1 ns > 0 sec) then return 1 ns;
+ elsif (1 us > 0 sec) then return 1 us;
+ elsif (1 ms > 0 sec) then return 1 ms;
+ else return 1 sec;
+ end if;
+ end function;
+
+ -- real division for physical types
+ -- ===========================================================================
+ function div(a : TIME; b : TIME) return REAL is
+ constant MTRIS : TIME := MinimalTimeResolutionInSimulation;
+ variable a_real : real;
+ variable b_real : real;
+ begin
+ -- Quartus-II work-around
+ if a < 1 us then
+ a_real := real(a / MTRIS);
+ elsif a < 1 ms then
+ a_real := real(a / (1000 * MTRIS)) * 1000.0;
+ elsif a < 1 sec then
+ a_real := real(a / (1000000 * MTRIS)) * 1000000.0;
+ else
+ a_real := real(a / (1000000000 * MTRIS)) * 1000000000.0;
+ end if;
+
+ if b < 1 us then
+ b_real := real(b / MTRIS);
+ elsif b < 1 ms then
+ b_real := real(b / (1000 * MTRIS)) * 1000.0;
+ elsif b < 1 sec then
+ b_real := real(b / (1000000 * MTRIS)) * 1000000.0;
+ else
+ b_real := real(b / (1000000000 * MTRIS)) * 1000000000.0;
+ end if;
+
+ return a_real / b_real;
+ end function;
+
+ function div(a : FREQ; b : FREQ) return REAL is
+ begin
+ return real(a / 1 Hz) / real(b / 1 Hz);
+ end function;
+
+ function div(a : BAUD; b : BAUD) return REAL is
+ begin
+ return real(a / 1 Bd) / real(b / 1 Bd);
+ end function;
+
+ function div(a : MEMORY; b : MEMORY) return REAL is
+ begin
+ return real(a / 1 Byte) / real(b / 1 Byte);
+ end function;
+
+ -- conversion functions
+ -- ===========================================================================
+ function to_time(f : FREQ) return TIME is
+ variable res : TIME;
+ begin
+ res := div(1000 MHz, f) * 1 ns;
+ if (POC_VERBOSE = TRUE) then
+ report "to_time: f= " & to_string(f, 3) & " return " & to_string(res, 3) severity note;
+ end if;
+ return res;
+ end function;
+
+ function to_freq(p : TIME) return FREQ is
+ variable res : FREQ;
+ begin
+ if (p <= 1 sec) then res := div(1 sec, p) * 1 Hz;
+ else report "to_freq: input period exceeds output frequency scale." severity failure;
+ end if;
+ if (POC_VERBOSE = TRUE) then
+ report "to_freq: p= " & to_string(p, 3) & " return " & to_string(res, 3) severity note;
+ end if;
+ return res;
+ end function;
+
+ function to_freq(br : BAUD) return FREQ is
+ variable res : FREQ;
+ begin
+ res := (br / 1 Bd) * 1 Hz;
+ if (POC_VERBOSE = TRUE) then
+ report "to_freq: br= " & to_string(br, 3) & " return " & to_string(res, 3) severity note;
+ end if;
+ return res;
+ end function;
+
+ function to_baud(str : STRING) return BAUD is
+ variable pos : INTEGER;
+ variable int : NATURAL;
+ variable base : POSITIVE;
+ variable frac : NATURAL;
+ variable digits : NATURAL;
+ begin
+ pos := str'low;
+ int := 0;
+ frac := 0;
+ digits := 0;
+ -- read integer part
+ for i in pos to str'high loop
+ if (chr_isDigit(str(i)) = TRUE) then int := int * 10 + to_digit_dec(str(i));
+ elsif (str(i) = '.') then pos := -i; exit;
+ elsif (str(i) = ' ') then pos := i; exit;
+ else pos := 0; exit;
+ end if;
+ end loop;
+ -- read fractional part
+ if ((pos < 0) and (-pos < str'high)) then
+ for i in -pos+1 to str'high loop
+ if ((frac = 0) and (str(i) = '0')) then next;
+ elsif (chr_isDigit(str(i)) = TRUE) then frac := frac * 10 + to_digit_dec(str(i));
+ elsif (str(i) = ' ') then digits := i + pos - 1; pos := i; exit;
+ else pos := 0; exit;
+ end if;
+ end loop;
+ end if;
+ -- abort if format is unknown
+ if (pos = 0) then report "to_baud: Unknown format" severity FAILURE; end if;
+ -- parse unit
+ pos := pos + 1;
+ if ((pos + 1 = str'high) and (str(pos to pos + 1) = "Bd")) then
+ return int * 1 Bd;
+ elsif (pos + 2 = str'high) then
+ if (str(pos to pos + 2) = "kBd") then
+ if (frac = 0) then return (int * 1 kBd);
+ elsif (digits <= 3) then return (int * 1 kBd) + (frac * 10**(3 - digits) * 1 Bd);
+ else return (int * 1 kBd) + (frac / 10**(digits - 3) * 100 Bd);
+ end if;
+ elsif (str(pos to pos + 2) = "MBd") then
+ if (frac = 0) then return (int * 1 kBd);
+ elsif (digits <= 3) then return (int * 1 MBd) + (frac * 10**(3 - digits) * 1 kBd);
+ elsif (digits <= 6) then return (int * 1 MBd) + (frac * 10**(6 - digits) * 1 Bd);
+ else return (int * 1 MBd) + (frac / 10**(digits - 6) * 100000 Bd);
+ end if;
+ elsif (str(pos to pos + 2) = "GBd") then
+ if (frac = 0) then return (int * 1 kBd);
+ elsif (digits <= 3) then return (int * 1 GBd) + (frac * 10**(3 - digits) * 1 MBd);
+ elsif (digits <= 6) then return (int * 1 GBd) + (frac * 10**(6 - digits) * 1 kBd);
+ elsif (digits <= 9) then return (int * 1 GBd) + (frac * 10**(9 - digits) * 1 Bd);
+ else return (int * 1 GBd) + (frac / 10**(digits - 9) * 100000000 Bd);
+ end if;
+ else
+ report "to_baud: Unknown unit." severity FAILURE;
+ end if;
+ else
+ report "to_baud: Unknown format" severity FAILURE;
+ end if;
+ end function;
+
+ -- if-then-else
+ -- ===========================================================================
+ function ite(cond : BOOLEAN; value1 : TIME; value2 : TIME) return TIME is
+ begin
+ if cond then
+ return value1;
+ else
+ return value2;
+ end if;
+ end function;
+
+ function ite(cond : BOOLEAN; value1 : FREQ; value2 : FREQ) return FREQ is
+ begin
+ if cond then
+ return value1;
+ else
+ return value2;
+ end if;
+ end function;
+
+ function ite(cond : BOOLEAN; value1 : BAUD; value2 : BAUD) return BAUD is
+ begin
+ if cond then
+ return value1;
+ else
+ return value2;
+ end if;
+ end function;
+
+ function ite(cond : BOOLEAN; value1 : MEMORY; value2 : MEMORY) return MEMORY is
+ begin
+ if cond then
+ return value1;
+ else
+ return value2;
+ end if;
+ end function;
+
+ -- min/ max for 2 arguments
+ -- ===========================================================================
+ -- Calculates: min(arg1, arg2) for times
+ function tmin(arg1 : TIME; arg2 : TIME) return TIME is
+ begin
+ if (arg1 < arg2) then return arg1; end if;
+ return arg2;
+ end function;
+
+ -- Calculates: min(arg1, arg2) for frequencies
+ function fmin(arg1 : FREQ; arg2 : FREQ) return FREQ is
+ begin
+ if (arg1 < arg2) then return arg1; end if;
+ return arg2;
+ end function;
+
+ -- Calculates: min(arg1, arg2) for symbols per second
+ function bmin(arg1 : BAUD; arg2 : BAUD) return BAUD is
+ begin
+ if (arg1 < arg2) then return arg1; end if;
+ return arg2;
+ end function;
+
+ -- Calculates: min(arg1, arg2) for memory
+ function mmin(arg1 : MEMORY; arg2 : MEMORY) return MEMORY is
+ begin
+ if (arg1 < arg2) then return arg1; end if;
+ return arg2;
+ end function;
+
+ -- Calculates: max(arg1, arg2) for times
+ function tmax(arg1 : TIME; arg2 : TIME) return TIME is
+ begin
+ if (arg1 > arg2) then return arg1; end if;
+ return arg2;
+ end function;
+
+ -- Calculates: max(arg1, arg2) for frequencies
+ function fmax(arg1 : FREQ; arg2 : FREQ) return FREQ is
+ begin
+ if (arg1 > arg2) then return arg1; end if;
+ return arg2;
+ end function;
+
+ -- Calculates: max(arg1, arg2) for symbols per second
+ function bmax(arg1 : BAUD; arg2 : BAUD) return BAUD is
+ begin
+ if (arg1 > arg2) then return arg1; end if;
+ return arg2;
+ end function;
+
+ -- Calculates: max(arg1, arg2) for memory
+ function mmax(arg1 : MEMORY; arg2 : MEMORY) return MEMORY is
+ begin
+ if (arg1 > arg2) then return arg1; end if;
+ return arg2;
+ end function;
+
+ -- min/max/sum as vector aggregation
+ -- ===========================================================================
+ -- Calculates: min(vec) for a time vector
+ function tmin(vec : T_TIMEVEC) return TIME is
+ variable res : TIME := TIME'high;
+ begin
+ for i in vec'range loop
+ if (vec(i) < res) then
+ res := vec(i);
+ end if;
+ end loop;
+ return res;
+ end;
+
+ -- Calculates: min(vec) for a frequency vector
+ function fmin(vec : T_FREQVEC) return FREQ is
+ variable res : FREQ := FREQ'high;
+ begin
+ for i in vec'range loop
+ if (integer(FREQ'pos(vec(i))) < integer(FREQ'pos(res))) then -- Quartus workaround
+ res := vec(i);
+ end if;
+ end loop;
+ return res;
+ end;
+
+ -- Calculates: min(vec) for a baud vector
+ function bmin(vec : T_BAUDVEC) return BAUD is
+ variable res : BAUD := BAUD'high;
+ begin
+ for i in vec'range loop
+ if (integer(BAUD'pos(vec(i))) < integer(BAUD'pos(res))) then -- Quartus workaround
+ res := vec(i);
+ end if;
+ end loop;
+ return res;
+ end;
+
+ -- Calculates: min(vec) for a memory vector
+ function mmin(vec : T_MEMVEC) return MEMORY is
+ variable res : MEMORY := MEMORY'high;
+ begin
+ for i in vec'range loop
+ if (integer(MEMORY'pos(vec(i))) < integer(MEMORY'pos(res))) then -- Quartus workaround
+ res := vec(i);
+ end if;
+ end loop;
+ return res;
+ end;
+
+ -- Calculates: max(vec) for a time vector
+ function tmax(vec : T_TIMEVEC) return TIME is
+ variable res : TIME := TIME'low;
+ begin
+ for i in vec'range loop
+ if (vec(i) > res) then
+ res := vec(i);
+ end if;
+ end loop;
+ return res;
+ end;
+
+ -- Calculates: max(vec) for a frequency vector
+ function fmax(vec : T_FREQVEC) return FREQ is
+ variable res : FREQ := FREQ'low;
+ begin
+ for i in vec'range loop
+ if (integer(FREQ'pos(vec(i))) > integer(FREQ'pos(res))) then -- Quartus workaround
+ res := vec(i);
+ end if;
+ end loop;
+ return res;
+ end;
+
+ -- Calculates: max(vec) for a baud vector
+ function bmax(vec : T_BAUDVEC) return BAUD is
+ variable res : BAUD := BAUD'low;
+ begin
+ for i in vec'range loop
+ if (integer(BAUD'pos(vec(i))) > integer(BAUD'pos(res))) then -- Quartus workaround
+ res := vec(i);
+ end if;
+ end loop;
+ return res;
+ end;
+
+ -- Calculates: max(vec) for a memory vector
+ function mmax(vec : T_MEMVEC) return MEMORY is
+ variable res : MEMORY := MEMORY'low;
+ begin
+ for i in vec'range loop
+ if (integer(MEMORY'pos(vec(i))) > integer(MEMORY'pos(res))) then -- Quartus workaround
+ res := vec(i);
+ end if;
+ end loop;
+ return res;
+ end;
+
+ -- Calculates: sum(vec) for a time vector
+ function tsum(vec : T_TIMEVEC) return TIME is
+ variable res : TIME := 0 fs;
+ begin
+ for i in vec'range loop
+ res := res + vec(i);
+ end loop;
+ return res;
+ end;
+
+ -- Calculates: sum(vec) for a frequency vector
+ function fsum(vec : T_FREQVEC) return FREQ is
+ variable res : FREQ := 0 Hz;
+ begin
+ for i in vec'range loop
+ res := res + vec(i);
+ end loop;
+ return res;
+ end;
+
+ -- Calculates: sum(vec) for a baud vector
+ function bsum(vec : T_BAUDVEC) return BAUD is
+ variable res : BAUD := 0 Bd;
+ begin
+ for i in vec'range loop
+ res := res + vec(i);
+ end loop;
+ return res;
+ end;
+
+ -- Calculates: sum(vec) for a memory vector
+ function msum(vec : T_MEMVEC) return MEMORY is
+ variable res : MEMORY := 0 Byte;
+ begin
+ for i in vec'range loop
+ res := res + vec(i);
+ end loop;
+ return res;
+ end;
+
+ -- convert standard types (NATURAL, REAL) to time (TIME)
+ -- ===========================================================================
+ function fs2Time(t_fs : INTEGER) return TIME is
+ begin
+ return t_fs * 1 fs;
+ end function;
+
+ function ps2Time(t_ps : INTEGER) return TIME is
+ begin
+ return t_ps * 1 ps;
+ end function;
+
+ function ns2Time(t_ns : INTEGER) return TIME is
+ begin
+ return t_ns * 1 ns;
+ end function;
+
+ function us2Time(t_us : INTEGER) return TIME is
+ begin
+ return t_us * 1 us;
+ end function;
+
+ function ms2Time(t_ms : INTEGER) return TIME is
+ begin
+ return t_ms * 1 ms;
+ end function;
+
+ function sec2Time(t_sec : INTEGER) return TIME is
+ begin
+ return t_sec * 1 sec;
+ end function;
+
+ function fs2Time(t_fs : REAL) return TIME is
+ begin
+ return t_fs * 1 fs;
+ end function;
+
+ function ps2Time(t_ps : REAL) return TIME is
+ begin
+ return t_ps * 1 ps;
+ end function;
+
+ function ns2Time(t_ns : REAL) return TIME is
+ begin
+ return t_ns * 1 ns;
+ end function;
+
+ function us2Time(t_us : REAL) return TIME is
+ begin
+ return t_us * 1 us;
+ end function;
+
+ function ms2Time(t_ms : REAL) return TIME is
+ begin
+ return t_ms * 1 ms;
+ end function;
+
+ function sec2Time(t_sec : REAL) return TIME is
+ begin
+ return t_sec * 1 sec;
+ end function;
+
+ -- convert standard types (NATURAL, REAL) to period (TIME)
+ -- ===========================================================================
+ function Hz2Time(f_Hz : NATURAL) return TIME is
+ begin
+ return 1 sec / f_Hz;
+ end function;
+
+ function kHz2Time(f_kHz : NATURAL) return TIME is
+ begin
+ return 1 ms / f_kHz;
+ end function;
+
+ function MHz2Time(f_MHz : NATURAL) return TIME
+ is
+ begin
+ return 1 us / f_MHz;
+ end function;
+
+ function GHz2Time(f_GHz : NATURAL) return TIME is
+ begin
+ return 1 ns / f_GHz;
+ end function;
+
+ function Hz2Time(f_Hz : REAL) return TIME is
+ begin
+ return 1 sec / f_Hz;
+ end function;
+
+ function kHz2Time(f_kHz : REAL) return TIME is
+ begin
+ return 1 ms / f_kHz;
+ end function;
+
+ function MHz2Time(f_MHz : REAL) return TIME is
+ begin
+ return 1 us / f_MHz;
+ end function;
+
+ function GHz2Time(f_GHz : REAL) return TIME is
+ begin
+ return 1 ns / f_GHz;
+ end function;
+
+ -- convert standard types (NATURAL, REAL) to frequency (FREQ)
+ -- ===========================================================================
+ function Hz2Freq(f_Hz : NATURAL) return FREQ is
+ begin
+ return f_Hz * 1 Hz;
+ end function;
+
+ function kHz2Freq(f_kHz : NATURAL) return FREQ is
+ begin
+ return f_kHz * 1 kHz;
+ end function;
+
+ function MHz2Freq(f_MHz : NATURAL) return FREQ is
+ begin
+ return f_MHz * 1 MHz;
+ end function;
+
+ function GHz2Freq(f_GHz : NATURAL) return FREQ is
+ begin
+ return f_GHz * 1 GHz;
+ end function;
+
+ function Hz2Freq(f_Hz : REAL) return FREQ is
+ begin
+ return f_Hz * 1 Hz;
+ end function;
+
+ function kHz2Freq(f_kHz : REAL )return FREQ is
+ begin
+ return f_kHz * 1 kHz;
+ end function;
+
+ function MHz2Freq(f_MHz : REAL )return FREQ is
+ begin
+ return f_MHz * 1 MHz;
+ end function;
+
+ function GHz2Freq(f_GHz : REAL )return FREQ is
+ begin
+ return f_GHz * 1 GHz;
+ end function;
+
+ -- convert physical types to standard type (REAL)
+ -- ===========================================================================
+ function to_real(t : TIME; scale : TIME) return REAL is
+ begin
+ if (scale = 1 fs) then return div(t, 1 fs);
+ elsif (scale = 1 ps) then return div(t, 1 ps);
+ elsif (scale = 1 ns) then return div(t, 1 ns);
+ elsif (scale = 1 us) then return div(t, 1 us);
+ elsif (scale = 1 ms) then return div(t, 1 ms);
+ elsif (scale = 1 sec) then return div(t, 1 sec);
+ else report "to_real: scale must have a value of '1 <unit>'" severity failure;
+ end if;
+ end;
+
+ function to_real(f : FREQ; scale : FREQ) return REAL is
+ begin
+ if (scale = 1 Hz) then return div(f, 1 Hz);
+ elsif (scale = 1 kHz) then return div(f, 1 kHz);
+ elsif (scale = 1 MHz) then return div(f, 1 MHz);
+ elsif (scale = 1 GHz) then return div(f, 1 GHz);
+-- elsif (scale = 1 THz) then return div(f, 1 THz);
+ else report "to_real: scale must have a value of '1 <unit>'" severity failure;
+ end if;
+ end;
+
+ function to_real(br : BAUD; scale : BAUD) return REAL is
+ begin
+ if (scale = 1 Bd) then return div(br, 1 Bd);
+ elsif (scale = 1 kBd) then return div(br, 1 kBd);
+ elsif (scale = 1 MBd) then return div(br, 1 MBd);
+ elsif (scale = 1 GBd) then return div(br, 1 GBd);
+ else report "to_real: scale must have a value of '1 <unit>'" severity failure;
+ end if;
+ end;
+
+ function to_real(mem : MEMORY; scale : MEMORY) return REAL is
+ begin
+ if (scale = 1 Byte) then return div(mem, 1 Byte);
+ elsif (scale = 1 KiB) then return div(mem, 1 KiB);
+ elsif (scale = 1 MiB) then return div(mem, 1 MiB);
+ elsif (scale = 1 GiB) then return div(mem, 1 GiB);
+ else report "to_real: scale must have a value of '1 <unit>'" severity failure;
+ end if;
+ end;
+
+ -- convert physical types to standard type (INTEGER)
+ -- ===========================================================================
+ function to_int(t : TIME; scale : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
+ begin
+ case RoundingStyle is
+ when ROUND_UP => return integer(ceil(to_real(t, scale)));
+ when ROUND_DOWN => return integer(floor(to_real(t, scale)));
+ when ROUND_TO_NEAREST => return integer(round(to_real(t, scale)));
+ when others => null;
+ end case;
+ report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
+ end;
+
+ function to_int(f : FREQ; scale : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
+ begin
+ case RoundingStyle is
+ when ROUND_UP => return integer(ceil(to_real(f, scale)));
+ when ROUND_DOWN => return integer(floor(to_real(f, scale)));
+ when ROUND_TO_NEAREST => return integer(round(to_real(f, scale)));
+ when others => null;
+ end case;
+ report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
+ end;
+
+ function to_int(br : BAUD; scale : BAUD; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
+ begin
+ case RoundingStyle is
+ when ROUND_UP => return integer(ceil(to_real(br, scale)));
+ when ROUND_DOWN => return integer(floor(to_real(br, scale)));
+ when ROUND_TO_NEAREST => return integer(round(to_real(br, scale)));
+ when others => null;
+ end case;
+ report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
+ end;
+
+ function to_int(mem : MEMORY; scale : MEMORY; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return INTEGER is
+ begin
+ case RoundingStyle is
+ when ROUND_UP => return integer(ceil(to_real(mem, scale)));
+ when ROUND_DOWN => return integer(floor(to_real(mem, scale)));
+ when ROUND_TO_NEAREST => return integer(round(to_real(mem, scale)));
+ when others => null;
+ end case;
+ report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
+ end;
+
+ -- calculate needed counter cycles to achieve a given 1. timing/delay and 2. frequency/period
+ -- ===========================================================================
+ -- @param Timing A given timing or delay, which should be achived
+ -- @param Clock_Period The period of the circuits clock
+ -- @RoundingStyle Default = round to nearest; other choises: ROUND_UP, ROUND_DOWN
+ function TimingToCycles(Timing : TIME; Clock_Period : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL is
+ variable res_real : REAL;
+ variable res_nat : NATURAL;
+ variable res_time : TIME;
+ variable res_dev : REAL;
+ begin
+ res_real := div(Timing, Clock_Period);
+ case RoundingStyle is
+ when ROUND_TO_NEAREST => res_nat := natural(round(res_real));
+ when ROUND_UP => res_nat := natural(ceil(res_real));
+ when ROUND_DOWN => res_nat := natural(floor(res_real));
+ when others => report "RoundingStyle '" & T_ROUNDING_STYLE'image(RoundingStyle) & "' not supported." severity failure;
+ end case;
+ res_time := CyclesToDelay(res_nat, Clock_Period);
+ res_dev := (div(res_time, Timing) - 1.0) * 100.0;
+
+ if (POC_VERBOSE = TRUE) then
+ report "TimingToCycles: " & CR &
+ " Timing: " & to_string(Timing, 3) & CR &
+ " Clock_Period: " & to_string(Clock_Period, 3) & CR &
+ " RoundingStyle: " & str_substr(T_ROUNDING_STYLE'image(RoundingStyle), 7) & CR &
+ " res_real = " & str_format(res_real, 3) & CR &
+ " => " & INTEGER'image(res_nat)
+ severity note;
+ end if;
+
+ if (C_PHYSICAL_REPORT_TIMING_DEVIATION = TRUE) then
+ report "TimingToCycles (timing deviation report): " & CR &
+ " timing to achieve: " & to_string(Timing, 3) & CR &
+ " calculated cycles: " & INTEGER'image(res_nat) & " cy" & CR &
+ " resulting timing: " & to_string(res_time, 3) & CR &
+ " deviation: " & to_string(res_time - Timing, 3) & " (" & str_format(res_dev, 2) & "%)"
+ severity note;
+ end if;
+
+ return res_nat;
+ end;
+
+ function TimingToCycles(Timing : TIME; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL is
+ begin
+ return TimingToCycles(Timing, to_time(Clock_Frequency), RoundingStyle);
+ end function;
+
+ function CyclesToDelay(Cycles : NATURAL; Clock_Period : TIME) return TIME is
+ begin
+ return Clock_Period * Cycles;
+ end function;
+
+ function CyclesToDelay(Cycles : NATURAL; Clock_Frequency : FREQ) return TIME is
+ begin
+ return CyclesToDelay(Cycles, to_time(Clock_Frequency));
+ end function;
+
+ -- convert and format physical types to STRING
+ function to_string(t : TIME; precision : NATURAL) return STRING is
+ variable tt : TIME;
+ variable unit : STRING(1 to 3) := (others => C_POC_NUL);
+ variable value : REAL;
+ begin
+ tt := abs t;
+ if (tt < 1 ps) then
+ unit(1 to 2) := "fs";
+ value := to_real(tt, 1 fs);
+ elsif (tt < 1 ns) then
+ unit(1 to 2) := "ps";
+ value := to_real(tt, 1 ps);
+ elsif (tt < 1 us) then
+ unit(1 to 2) := "ns";
+ value := to_real(tt, 1 ns);
+ elsif (tt < 1 ms) then
+ unit(1 to 2) := "us";
+ value := to_real(tt, 1 us);
+ elsif (tt < 1 sec) then
+ unit(1 to 2) := "ms";
+ value := to_real(tt, 1 ms);
+ else
+ unit := "sec";
+ value := to_real(tt, 1 sec);
+ end if;
+
+ return ite(t >= 0 fs, str_format(value, precision) & " " & str_trim(unit),
+ '-' & str_format(value, precision) & " " & str_trim(unit));
+ end function;
+
+ function to_string(f : FREQ; precision : NATURAL) return STRING is
+ variable unit : STRING(1 to 3) := (others => C_POC_NUL);
+ variable value : REAL;
+ begin
+ if (f < 1 kHz) then
+ unit(1 to 2) := "Hz";
+ value := to_real(f, 1 Hz);
+ elsif (f < 1 MHz) then
+ unit := "kHz";
+ value := to_real(f, 1 kHz);
+ elsif (f < 1 GHz) then
+ unit := "MHz";
+ value := to_real(f, 1 MHz);
+ else
+ unit := "GHz";
+ value := to_real(f, 1 GHz);
+ end if;
+
+ return str_format(value, precision) & " " & str_trim(unit);
+ end function;
+
+ function to_string(br : BAUD; precision : NATURAL) return STRING is
+ variable unit : STRING(1 to 3) := (others => C_POC_NUL);
+ variable value : REAL;
+ begin
+ if (br < 1 kBd) then
+ unit(1 to 2) := "Bd";
+ value := to_real(br, 1 Bd);
+ elsif (br < 1 MBd) then
+ unit := "kBd";
+ value := to_real(br, 1 kBd);
+ elsif (br < 1 GBd) then
+ unit := "MBd";
+ value := to_real(br, 1 MBd);
+ else
+ unit := "GBd";
+ value := to_real(br, 1 GBd);
+ end if;
+
+ return str_format(value, precision) & " " & str_trim(unit);
+ end function;
+
+ function to_string(mem : MEMORY; precision : NATURAL) return STRING is
+ variable unit : STRING(1 to 3) := (others => C_POC_NUL);
+ variable value : REAL;
+ begin
+ if (mem < 1 KiB) then
+ unit(1) := 'B';
+ value := to_real(mem, 1 Byte);
+ elsif (mem < 1 MiB) then
+ unit := "KiB";
+ value := to_real(mem, 1 KiB);
+ elsif (mem < 1 GiB) then
+ unit := "MiB";
+ value := to_real(mem, 1 MiB);
+ else
+ unit := "GiB";
+ value := to_real(mem, 1 GiB);
+ end if;
+
+ return str_format(value, precision) & " " & str_trim(unit);
+ end function;
+
+end package body;
diff --git a/testsuite/gna/bug037/sim_global.v08.vhdl b/testsuite/gna/bug037/sim_global.v08.vhdl new file mode 100644 index 000000000..78a94b1a9 --- /dev/null +++ b/testsuite/gna/bug037/sim_global.v08.vhdl @@ -0,0 +1,40 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+--
+-- =============================================================================
+-- Authors: Patrick Lehmann
+--
+-- Package: Global simulation constants and shared varibales.
+--
+-- Description:
+-- ------------------------------------
+-- TODO
+--
+-- License:
+-- =============================================================================
+-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
+-- Chair for VLSI-Design, Diagnostics and Architecture
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+
+library PoC;
+use PoC.sim_protected.all;
+
+
+package sim_global is
+ -- The default global status objects.
+ -- ===========================================================================
+ shared variable globalSimulationStatus : T_SIM_STATUS;
+end package;
diff --git a/testsuite/gna/bug037/sim_protected.v08.vhdl b/testsuite/gna/bug037/sim_protected.v08.vhdl new file mode 100644 index 000000000..853ed735c --- /dev/null +++ b/testsuite/gna/bug037/sim_protected.v08.vhdl @@ -0,0 +1,225 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+--
+-- =============================================================================
+-- Authors: Patrick Lehmann
+-- Thomas B. Preusser
+--
+-- Package: Simulation constants, functions and utilities.
+--
+-- Description:
+-- ------------------------------------
+-- TODO
+--
+-- License:
+-- =============================================================================
+-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
+-- Chair for VLSI-Design, Diagnostics and Architecture
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+
+use STD.TextIO.all;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+library PoC;
+use PoC.utils.all;
+use PoC.strings.all;
+use PoC.vectors.all;
+use PoC.physical.all;
+
+use PoC.sim_types.all;
+
+
+package sim_protected is
+ -- Simulation Task and Status Management
+ -- ===========================================================================
+ type T_SIM_STATUS is protected
+ -- Initializer and Finalizer
+ procedure initialize;
+ procedure finalize;
+
+ -- Assertions
+ procedure fail(Message : STRING := "");
+ procedure assertion(Condition : BOOLEAN; Message : STRING := "");
+ procedure writeMessage(Message : STRING);
+ procedure writeReport;
+
+ -- Process Management
+ -- impure function registerProcess(Name : STRING; InstanceName : STRING) return T_SIM_PROCESS_ID;
+ impure function registerProcess(Name : STRING) return T_SIM_PROCESS_ID;
+ procedure deactivateProcess(procID : T_SIM_PROCESS_ID);
+
+ -- Test Management
+ impure function createTest(Name : STRING) return T_SIM_TEST_ID;
+
+ -- Run Management
+ procedure stopAllClocks;
+ impure function isStopped return BOOLEAN;
+ end protected;
+end package;
+
+
+package body sim_protected is
+ -- Simulation process and Status Management
+ -- ===========================================================================
+ type T_SIM_STATUS is protected body
+ -- status
+ variable IsInitialized : BOOLEAN := FALSE;
+ variable IsFinalized : BOOLEAN := FALSE;
+
+ -- Internal state variable to log a failure condition for final reporting.
+ -- Once de-asserted, this variable will never return to a value of true.
+ variable Passed : BOOLEAN := TRUE;
+ variable AssertCount : NATURAL := 0;
+ variable FailedAssertCount : NATURAL := 0;
+
+ -- Clock Management
+ variable MainClockEnable : BOOLEAN := TRUE;
+
+ -- Process Management
+ variable ProcessCount : NATURAL := 0;
+ variable ActiveProcessCount : NATURAL := 0;
+ variable Processes : T_SIM_PROCESS_VECTOR(T_SIM_PROCESS_ID);
+
+ -- Test Management
+ variable TestCount : NATURAL := 0;
+ variable Tests : T_SIM_TEST_VECTOR(T_SIM_TEST_ID);
+
+ -- Initializer
+ procedure initialize is
+ begin
+ IsInitialized := TRUE;
+ end procedure;
+
+ procedure finalize is
+ begin
+ if (IsFinalized = FALSE) then
+ if (ActiveProcessCount = 0) then
+ writeReport;
+ IsFinalized := TRUE;
+ end if;
+ end if;
+ end procedure;
+
+ procedure fail(Message : STRING := "") is
+ begin
+ if (Message'length > 0) then
+ report Message severity ERROR;
+ end if;
+ Passed := FALSE;
+ end procedure;
+
+ procedure assertion(condition : BOOLEAN; Message : STRING := "") is
+ begin
+ AssertCount := AssertCount + 1;
+ if (condition = FALSE) then
+ fail(Message);
+ FailedAssertCount := FailedAssertCount + 1;
+ end if;
+ end procedure;
+
+ procedure writeMessage(Message : STRING) is
+ variable LineBuffer : LINE;
+ begin
+ write(LineBuffer, Message);
+ writeline(output, LineBuffer);
+ end procedure;
+
+ procedure writeReport is
+ variable LineBuffer : LINE;
+ begin
+ write(LineBuffer, (CR & STRING'("========================================")));
+ write(LineBuffer, (CR & STRING'("POC TESTBENCH REPORT")));
+ write(LineBuffer, (CR & STRING'("========================================")));
+ write(LineBuffer, (CR & STRING'("Assertions ") & INTEGER'image(AssertCount)));
+ write(LineBuffer, (CR & STRING'(" failed ") & INTEGER'image(FailedAssertCount)));
+ write(LineBuffer, (CR & STRING'("Processes ") & INTEGER'image(ProcessCount)));
+ write(LineBuffer, (CR & STRING'(" active ") & INTEGER'image(ActiveProcessCount)));
+ for i in 0 to ProcessCount - 1 loop
+ if (Processes(i).Status = SIM_PROCESS_STATUS_ACTIVE) then
+ write(LineBuffer, (CR & STRING'(" ") & str_trim(Processes(i).Name)));
+ end if;
+ end loop;
+ write(LineBuffer, (CR & STRING'("Tests ") & INTEGER'image(TestCount)));
+ for i in 0 to TestCount - 1 loop
+ write(LineBuffer, (CR & STRING'(" ") & str_ralign(INTEGER'image(i), log10ceil(T_SIM_TEST_ID'high)) & ": " & str_trim(Tests(i).Name)));
+ end loop;
+ write(LineBuffer, (CR & STRING'("========================================")));
+ if (AssertCount = 0) then
+ write(LineBuffer, (CR & STRING'("SIMULATION RESULT = NO ASSERTS")));
+ elsif (Passed = TRUE) then
+ write(LineBuffer, (CR & STRING'("SIMULATION RESULT = PASSED")));
+ else
+ write(LineBuffer, (CR & STRING'("SIMULATION RESULT = FAILED")));
+ end if;
+ write(LineBuffer, (CR & STRING'("========================================")));
+ writeline(output, LineBuffer);
+ end procedure;
+
+ -- impure function registerProcess(Name : STRING; InstanceName : STRING) return T_SIM_PROCESS_ID is
+ impure function registerProcess(Name : STRING) return T_SIM_PROCESS_ID is
+ variable Proc : T_SIM_PROCESS;
+ begin
+ Proc.ID := ProcessCount;
+ Proc.Name := resize(Name, T_SIM_PROCESS_NAME'length);
+ -- Proc.InstanceName := resize(InstanceName, T_SIM_PROCESS_INSTNAME'length);
+ Proc.Status := SIM_PROCESS_STATUS_ACTIVE;
+
+ Processes(Proc.ID) := Proc;
+ ProcessCount := ProcessCount + 1;
+ ActiveProcessCount := ActiveProcessCount + 1;
+ return Proc.ID;
+ end function;
+
+ procedure deactivateProcess(ProcID : T_SIM_PROCESS_ID) is
+ variable hasActiveProcesses : BOOLEAN := FALSE;
+ begin
+ if (ProcID < ProcessCount) then
+ if (Processes(ProcID).Status = SIM_PROCESS_STATUS_ACTIVE) then
+ Processes(ProcID).Status := SIM_PROCESS_STATUS_ENDED;
+ ActiveProcessCount := ActiveProcessCount - 1;
+ end if;
+ end if;
+
+ if (ActiveProcessCount = 0) then
+ stopAllClocks;
+ end if;
+ end procedure;
+
+ impure function createTest(Name : STRING) return T_SIM_TEST_ID is
+ variable Test : T_SIM_TEST;
+ begin
+ Test.ID := TestCount;
+ Test.Name := resize(Name, T_SIM_TEST_NAME'length);
+ Test.Status := SIM_TEST_STATUS_ACTIVE;
+
+ Tests(Test.ID) := Test;
+ TestCount := TestCount + 1;
+ return Test.ID;
+ end function;
+
+ procedure stopAllClocks is
+ begin
+ MainClockEnable := FALSE;
+ end procedure;
+
+ impure function isStopped return BOOLEAN is
+ begin
+ return not MainClockEnable;
+ end function;
+ end protected body;
+end package body;
diff --git a/testsuite/gna/bug037/sim_simulation.v08.vhdl b/testsuite/gna/bug037/sim_simulation.v08.vhdl new file mode 100644 index 000000000..8b0efea3f --- /dev/null +++ b/testsuite/gna/bug037/sim_simulation.v08.vhdl @@ -0,0 +1,440 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+--
+-- =============================================================================
+-- Authors: Patrick Lehmann
+-- Thomas B. Preusser
+--
+-- Package: Simulation constants, functions and utilities.
+--
+-- Description:
+-- ------------------------------------
+-- TODO
+--
+-- License:
+-- =============================================================================
+-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
+-- Chair for VLSI-Design, Diagnostics and Architecture
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use IEEE.math_real.all;
+
+library PoC;
+use PoC.utils.all;
+-- use PoC.strings.all;
+use PoC.vectors.all;
+use PoC.physical.all;
+
+use PoC.sim_global.all;
+use PoC.sim_types.all;
+use PoC.sim_protected.all;
+
+
+package simulation is
+ -- Legacy interface for pre VHDL-2002
+ -- ===========================================================================
+ procedure simInitialize;
+ procedure simFinalize;
+
+ impure function simCreateTest(Name : STRING) return T_SIM_TEST_ID;
+ impure function simRegisterProcess(Name : STRING) return T_SIM_PROCESS_ID;
+ procedure simDeactivateProcess(ProcID : T_SIM_PROCESS_ID);
+
+ impure function simIsStopped return BOOLEAN;
+
+ procedure simWriteMessage(Message : in STRING := "");
+
+ -- The testbench is marked as failed. If a message is provided, it is
+ -- reported as an error.
+ procedure simFail(Message : in STRING := "");
+
+ -- If the passed condition has evaluated false, the testbench is marked
+ -- as failed. In this case, the optional message will be reported as an
+ -- error if one was provided.
+ procedure simAssertion(cond : in BOOLEAN; Message : in STRING := "");
+
+ -- Random Numbers
+ -- ===========================================================================
+ type T_SIM_SEED is record
+ Seed1 : INTEGER;
+ Seed2 : INTEGER;
+ end record;
+
+ procedure initializeSeed(Seed : inout T_SIM_SEED);
+ procedure getUniformDistibutedRandomValue(Seed : inout T_SIM_SEED; Value : inout REAL; Minimum : in REAL; Maximum : in REAL);
+ procedure getNormalDistibutedRandomValue(Seed : inout T_SIM_SEED; Value : inout REAL; StandardDeviation : in REAL := 1.0; Mean : in REAL := 0.0);
+ procedure getNormalDistibutedRandomValue(Seed : inout T_SIM_SEED; Value : inout REAL; StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL);
+
+ -- clock generation
+ -- ===========================================================================
+ procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant Phase : in T_PHASE := 0 deg; constant DutyCycle : in T_DutyCycle := 50 percent; constant Wander : in T_WANDER := 0 permil);
+ procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant Phase : in T_PHASE := 0 deg; constant DutyCycle : in T_DutyCycle := 50 percent; constant Wander : in T_WANDER := 0 permil);
+ procedure simWaitUntilRisingEdge(signal Clock : in STD_LOGIC; constant Times : in POSITIVE);
+ procedure simWaitUntilFallingEdge(signal Clock : in STD_LOGIC; constant Times : in POSITIVE);
+
+ procedure simGenerateClock2(signal Clock : out STD_LOGIC; signal Debug : out INTEGER; constant Period : in TIME);
+
+ -- waveform generation
+ -- ===========================================================================
+ procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform: T_TIMEVEC; InitialValue : BOOLEAN);
+ procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0');
+ procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0');
+ procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8);
+ procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16);
+ procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24);
+ procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32);
+ procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48);
+ procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64);
+
+ function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC;
+
+
+ -- TODO: integrate VCD simulation functions and procedures from sim_value_change_dump.vhdl here
+
+ -- checksum functions
+ -- ===========================================================================
+ -- TODO: move checksum functions here
+end package;
+
+
+package body simulation is
+ -- legacy procedures
+ -- ===========================================================================
+ -- TODO: undocumented group
+ procedure simInitialize is
+ begin
+ globalSimulationStatus.initialize;
+ end procedure;
+
+ procedure simFinalize is
+ begin
+ globalSimulationStatus.finalize;
+ end procedure;
+
+ impure function simCreateTest(Name : STRING) return T_SIM_TEST_ID is
+ begin
+ return globalSimulationStatus.createTest(Name);
+ end function;
+
+ impure function simRegisterProcess(Name : STRING) return T_SIM_PROCESS_ID is
+ begin
+ return globalSimulationStatus.registerProcess(Name);
+ end function;
+
+ procedure simDeactivateProcess(ProcID : T_SIM_PROCESS_ID) is
+ begin
+ globalSimulationStatus.deactivateProcess(ProcID);
+ end procedure;
+
+ impure function simIsStopped return BOOLEAN is
+ begin
+ return globalSimulationStatus.isStopped;
+ end function;
+
+ -- TODO: undocumented group
+ procedure simWriteMessage(Message : in STRING := "") is
+ begin
+ globalSimulationStatus.writeMessage(Message);
+ end procedure;
+
+ procedure simFail(Message : in STRING := "") is
+ begin
+ globalSimulationStatus.fail(Message);
+ end procedure;
+
+ procedure simAssertion(cond : in BOOLEAN; Message : in STRING := "") is
+ begin
+ globalSimulationStatus.assertion(cond, Message);
+ end procedure;
+
+
+ -- ===========================================================================
+ -- Random Numbers
+ -- ===========================================================================
+ procedure initializeSeed(Seed : inout T_SIM_SEED) is
+ begin
+ Seed.Seed1 := 5;
+ Seed.Seed2 := 3423;
+ end procedure;
+
+ procedure getUniformDistibutedRandomValue(Seed : inout T_SIM_SEED; Value : inout REAL; Minimum : in REAL; Maximum : in REAL) is
+ variable rand : REAL;
+ begin
+ if (Maximum < Minimum) then report "getUniformDistibutedRandomValue: Maximum must be greater than Minimum." severity FAILURE; end if;
+ ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand);
+ Value := scale(rand, Minimum, Maximum);
+ end procedure ;
+
+ procedure getNormalDistibutedRandomValue(Seed : inout T_SIM_SEED; Value : inout REAL; StandardDeviation : in REAL := 1.0; Mean : in REAL := 0.0) is
+ variable rand1 : REAL;
+ variable rand2 : REAL;
+ begin
+ if StandardDeviation < 0.0 then report "getNormalDistibutedRandomValue: Standard deviation must be >= 0.0" severity FAILURE; end if;
+ -- Box Muller transformation
+ ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand1);
+ ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand2);
+ -- standard normal distribution: mean 0, variance 1
+ Value := StandardDeviation * (sqrt(-2.0 * log(rand1)) * cos(MATH_2_PI * rand2)) + Mean;
+ end procedure;
+
+ procedure getNormalDistibutedRandomValue(Seed : inout T_SIM_SEED; Value : inout REAL; StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL) is
+ variable rand : REAL;
+ begin
+ if (Maximum < Minimum) then report "getUniformDistibutedRandomValue: Maximum must be greater than Minimum." severity FAILURE; end if;
+ if StandardDeviation < 0.0 then report "getNormalDistibutedRandomValue: Standard deviation must be >= 0.0" severity FAILURE; end if;
+ while (TRUE) loop
+ getNormalDistibutedRandomValue(Seed, rand, StandardDeviation, Mean);
+ exit when ((Minimum <= rand) and (rand <= Maximum));
+ end loop;
+ Value := rand;
+ end procedure;
+
+ -- clock generation
+ -- ===========================================================================
+ procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant Phase : in T_PHASE := 0 deg; constant DutyCycle : in T_DUTYCYCLE := 50 percent; constant Wander : in T_WANDER := 0 permil) is
+ constant Period : TIME := to_time(Frequency);
+ begin
+ simGenerateClock(Clock, Period, Phase, DutyCycle, Wander);
+ end procedure;
+
+ procedure simGenerateClock(
+ signal Clock : out STD_LOGIC;
+ constant Period : in TIME;
+ constant Phase : in T_PHASE := 0 deg;
+ constant DutyCycle : in T_DUTYCYCLE := 50 percent;
+ constant Wander : in T_WANDER := 0 permil
+ ) is
+ constant NormalizedPhase : T_PHASE := ite((Phase >= 0 deg), Phase, Phase + 360 deg); -- move Phase into the range of 0° to 360°
+ constant PhaseAsFactor : REAL := real(NormalizedPhase / 1 second) / 1296000.0; -- 1,296,000 = 3,600 seconds * 360 degree per cycle
+ constant WanderAsFactor : REAL := real(Wander / 1 ppb) / 1.0e9;
+ constant DutyCycleAsFactor : REAL := real(DutyCycle / 1 permil) / 1000.0;
+ constant Delay : TIME := Period * PhaseAsFactor;
+ constant TimeHigh : TIME := Period * DutyCycleAsFactor + (Period * (WanderAsFactor / 2.0)); -- add 50% wander to the high level
+ constant TimeLow : TIME := Period - TimeHigh + (Period * WanderAsFactor); -- and 50% to the low level
+ constant ClockAfterRun_cy : POSITIVE := 1;
+ begin
+ report "simGenerateClock: (Instance: '" & Clock'instance_name & "')" & CR &
+ "Period: " & TIME'image(Period) & CR &
+ "Phase: " & T_PHASE'image(Phase) & CR &
+ "DutyCycle: " & T_DUTYCYCLE'image(DutyCycle) & CR &
+ "PhaseAsFactor: " & REAL'image(PhaseAsFactor) & CR &
+ "WanderAsFactor: " & REAL'image(WanderAsFactor) & CR &
+ "DutyCycleAsFactor: " & REAL'image(DutyCycleAsFactor) & CR &
+ "Delay: " & TIME'image(Delay) & CR &
+ "TimeHigh: " & TIME'image(TimeHigh) & CR &
+ "TimeLow: " & TIME'image(TimeLow)
+ severity NOTE;
+
+ if (Delay = 0 ns) then
+ null;
+ elsif (Delay <= TimeLow) then
+ Clock <= '0';
+ wait for Delay;
+ else
+ Clock <= '1';
+ wait for Delay - TimeLow;
+ Clock <= '0';
+ wait for TimeLow;
+ end if;
+ Clock <= '1';
+ while (not globalSimulationStatus.isStopped) loop
+ wait for TimeHigh;
+ Clock <= '0';
+ wait for TimeLow;
+ Clock <= '1';
+ end loop;
+ -- create N more cycles to allow other processes to recognize the stop condition (clock after run)
+ for i in 1 to ClockAfterRun_cy loop
+ wait for TimeHigh;
+ Clock <= '0';
+ wait for TimeLow;
+ Clock <= '1';
+ end loop;
+ Clock <= '0';
+ end procedure;
+
+ type T_SIM_NORMAL_DIST_PARAMETER is record
+ StandardDeviation : REAL;
+ Mean : REAL;
+ end record;
+ type T_JITTER_DISTRIBUTION is array (NATURAL range <>) of T_SIM_NORMAL_DIST_PARAMETER;
+
+ procedure simGenerateClock2(signal Clock : out STD_LOGIC; signal Debug : out INTEGER; constant Period : in TIME) is
+ constant TimeHigh : TIME := Period * 0.5;
+ constant TimeLow : TIME := Period - TimeHigh;
+ constant JitterPeakPeak : REAL := 0.1; -- UI
+ constant JitterAsFactor : REAL := JitterPeakPeak / 4.0; -- Maximum jitter per edge
+ constant JitterDistribution : T_JITTER_DISTRIBUTION := (0 => (0.6, 0.0)); --((0.2, -0.3), (0.3, -0.1), (0.5, 0.0), (0.3, 0.1), (0.2, 0.3));
+ variable Seed : T_SIM_SEED;
+ variable rand : REAL;
+ variable sum : REAL;
+ variable Jitter : REAL;
+ begin
+ Clock <= '1';
+ initializeSeed(Seed);
+
+ while (not globalSimulationStatus.isStopped) loop
+ sum := 0.0;
+ for i in JitterDistribution'range loop
+ getNormalDistibutedRandomValue(Seed, rand, JitterDistribution(i).StandardDeviation, JitterDistribution(i).Mean, -1.0, 1.0);
+ sum := sum + rand;
+ end loop;
+ Debug <= integer(sum * 1000.0);
+
+ Jitter := JitterAsFactor * sum;
+
+ -- Debug <= integer(rand * 256.0 + 256.0);
+ wait for TimeHigh + (Period * Jitter);
+ Clock <= '0';
+ wait for TimeLow + (Period * Jitter);
+ Clock <= '1';
+ end loop;
+ Clock <= '0';
+ end procedure;
+
+ procedure simWaitUntilRisingEdge(signal Clock : in STD_LOGIC; constant Times : in POSITIVE) is
+ begin
+ for i in 1 to Times loop
+ wait until rising_edge(Clock);
+ exit when globalSimulationStatus.isStopped;
+ end loop;
+ end procedure;
+
+ procedure simWaitUntilFallingEdge(signal Clock : in STD_LOGIC; constant Times : in POSITIVE) is
+ begin
+ for i in 1 to Times loop
+ wait until falling_edge(Clock);
+ exit when globalSimulationStatus.isStopped;
+ end loop;
+ end procedure;
+
+ -- waveform generation
+ -- ===========================================================================
+ procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform : T_TIMEVEC; InitialValue : BOOLEAN) is
+ variable State : BOOLEAN := InitialValue;
+ begin
+ Wave <= State;
+ for i in Waveform'range loop
+ wait for Waveform(i);
+ State := not State;
+ Wave <= State;
+ exit when globalSimulationStatus.isStopped;
+ end loop;
+ end procedure;
+
+ procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0') is
+ variable State : STD_LOGIC := InitialValue;
+ begin
+ Wave <= State;
+ for i in Waveform'range loop
+ wait for Waveform(i);
+ State := not State;
+ Wave <= State;
+ exit when globalSimulationStatus.isStopped;
+ end loop;
+ end procedure;
+
+ procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0') is
+ begin
+ Wave <= InitialValue;
+ for i in Waveform'range loop
+ wait for Waveform(i).Delay;
+ Wave <= Waveform(i).Value;
+ exit when globalSimulationStatus.isStopped;
+ end loop;
+ end procedure;
+
+ procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8) is
+ begin
+ Wave <= InitialValue;
+ for i in Waveform'range loop
+ wait for Waveform(i).Delay;
+ Wave <= Waveform(i).Value;
+ exit when globalSimulationStatus.isStopped;
+ end loop;
+ end procedure;
+
+ procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16) is
+ begin
+ Wave <= InitialValue;
+ for i in Waveform'range loop
+ wait for Waveform(i).Delay;
+ Wave <= Waveform(i).Value;
+ exit when globalSimulationStatus.isStopped;
+ end loop;
+ end procedure;
+
+ procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24) is
+ begin
+ Wave <= InitialValue;
+ for i in Waveform'range loop
+ wait for Waveform(i).Delay;
+ Wave <= Waveform(i).Value;
+ exit when globalSimulationStatus.isStopped;
+ end loop;
+ end procedure;
+
+ procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32) is
+ begin
+ Wave <= InitialValue;
+ for i in Waveform'range loop
+ wait for Waveform(i).Delay;
+ Wave <= Waveform(i).Value;
+ exit when globalSimulationStatus.isStopped;
+ end loop;
+ end procedure;
+
+ procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48) is
+ begin
+ Wave <= InitialValue;
+ for i in Waveform'range loop
+ wait for Waveform(i).Delay;
+ Wave <= Waveform(i).Value;
+ exit when globalSimulationStatus.isStopped;
+ end loop;
+ end procedure;
+
+ procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64) is
+ begin
+ Wave <= InitialValue;
+ for i in Waveform'range loop
+ wait for Waveform(i).Delay;
+ Wave <= Waveform(i).Value;
+ exit when globalSimulationStatus.isStopped;
+ end loop;
+ end procedure;
+
+ function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC is
+ variable p : TIME;
+ variable rp : TIME;
+ begin
+ -- WORKAROUND: for QuestaSim/ModelSim
+ -- Version: 10.4c
+ -- Issue:
+ -- return (0 => Pause, 1 => ResetPulse); always evaluates to (0 ns, 10 ns),
+ -- regardless of the passed function parameters
+ p := Pause;
+ rp := ResetPulse;
+ return (0 => p, 1 => rp);
+ end function;
+
+ -- checksum functions
+ -- ===========================================================================
+ -- TODO: move checksum functions here
+end package body;
diff --git a/testsuite/gna/bug037/sim_types.vhdl b/testsuite/gna/bug037/sim_types.vhdl new file mode 100644 index 000000000..8d5aaa5b9 --- /dev/null +++ b/testsuite/gna/bug037/sim_types.vhdl @@ -0,0 +1,159 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+--
+-- =============================================================================
+-- Authors: Patrick Lehmann
+-- Thomas B. Preusser
+--
+-- Package: Simulation constants, functions and utilities.
+--
+-- Description:
+-- ------------------------------------
+-- TODO
+--
+-- License:
+-- =============================================================================
+-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
+-- Chair for VLSI-Design, Diagnostics and Architecture
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+
+use STD.TextIO.all;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+library PoC;
+-- use PoC.utils.all;
+-- use PoC.strings.all;
+use PoC.vectors.all;
+-- use PoC.physical.all;
+
+
+package sim_types is
+ -- Simulation Task and Status Management
+ -- ===========================================================================
+ subtype T_SIM_PROCESS_ID is NATURAL range 0 to 1023;
+ subtype T_SIM_PROCESS_NAME is STRING(1 to 64);
+ subtype T_SIM_PROCESS_INSTNAME is STRING(1 to 256);
+
+ type T_SIM_PROCESS_STATUS is (
+ SIM_PROCESS_STATUS_ACTIVE,
+ SIM_PROCESS_STATUS_ENDED
+ );
+
+ type T_SIM_PROCESS is record
+ ID : T_SIM_PROCESS_ID;
+ Name : T_SIM_PROCESS_NAME;
+ InstanceName : T_SIM_PROCESS_INSTNAME;
+ Status : T_SIM_PROCESS_STATUS;
+ end record;
+ type T_SIM_PROCESS_VECTOR is array(NATURAL range <>) of T_SIM_PROCESS;
+
+ subtype T_SIM_TEST_ID is NATURAL range 0 to 1023;
+ subtype T_SIM_TEST_NAME is STRING(1 to 256);
+
+ type T_SIM_TEST_STATUS is (
+ SIM_TEST_STATUS_ACTIVE,
+ SIM_TEST_STATUS_ENDED
+ );
+
+ type T_SIM_TEST is record
+ ID : T_SIM_TEST_ID;
+ Name : T_SIM_TEST_NAME;
+ Status : T_SIM_TEST_STATUS;
+ end record;
+ type T_SIM_TEST_VECTOR is array(NATURAL range <>) of T_SIM_TEST;
+
+ -- clock generation
+ -- ===========================================================================
+ -- type T_PERCENT is INTEGER'range units
+ type T_PERCENT is range INTEGER'low to INTEGER'high units
+ ppb;
+ ppm = 1000 ppb;
+ permil = 1000 ppm;
+ percent = 10 permil;
+ one = 100 percent;
+ end units;
+ subtype T_WANDER is T_PERCENT range -1 one to 1 one;
+ subtype T_DUTYCYCLE is T_PERCENT range 0 ppb to 1 one;
+
+ type T_DEGREE is range INTEGER'low to INTEGER'high units
+ second;
+ minute = 60 second;
+ deg = 60 minute;
+ end units;
+ subtype T_PHASE is T_DEGREE range -360 deg to 360 deg;
+
+ function ite(cond : BOOLEAN; value1 : T_DEGREE; value2 : T_DEGREE) return T_DEGREE;
+
+ -- waveform generation
+ -- ===========================================================================
+ type T_SIM_WAVEFORM_TUPLE_SL is record
+ Delay : TIME;
+ Value : STD_LOGIC;
+ end record;
+
+ type T_SIM_WAVEFORM_TUPLE_SLV_8 is record
+ Delay : TIME;
+ Value : T_SLV_8;
+ end record;
+
+ type T_SIM_WAVEFORM_TUPLE_SLV_16 is record
+ Delay : TIME;
+ Value : T_SLV_16;
+ end record;
+
+ type T_SIM_WAVEFORM_TUPLE_SLV_24 is record
+ Delay : TIME;
+ Value : T_SLV_24;
+ end record;
+
+ type T_SIM_WAVEFORM_TUPLE_SLV_32 is record
+ Delay : TIME;
+ Value : T_SLV_32;
+ end record;
+
+ type T_SIM_WAVEFORM_TUPLE_SLV_48 is record
+ Delay : TIME;
+ Value : T_SLV_48;
+ end record;
+
+ type T_SIM_WAVEFORM_TUPLE_SLV_64 is record
+ Delay : TIME;
+ Value : T_SLV_64;
+ end record;
+
+ type T_SIM_WAVEFORM_SL is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SL;
+ type T_SIM_WAVEFORM_SLV_8 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_8;
+ type T_SIM_WAVEFORM_SLV_16 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_16;
+ type T_SIM_WAVEFORM_SLV_24 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_24;
+ type T_SIM_WAVEFORM_SLV_32 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_32;
+ type T_SIM_WAVEFORM_SLV_48 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_48;
+ type T_SIM_WAVEFORM_SLV_64 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_64;
+
+end package;
+
+
+package body sim_types is
+ function ite(cond : BOOLEAN; value1 : T_DEGREE; value2 : T_DEGREE) return T_DEGREE is
+ begin
+ if cond then
+ return value1;
+ else
+ return value2;
+ end if;
+ end function;
+end package body;
diff --git a/testsuite/gna/bug037/strings.vhdl b/testsuite/gna/bug037/strings.vhdl new file mode 100644 index 000000000..d105c5b99 --- /dev/null +++ b/testsuite/gna/bug037/strings.vhdl @@ -0,0 +1,936 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+--
+-- ============================================================================
+-- Authors: Thomas B. Preusser
+-- Martin Zabel
+-- Patrick Lehmann
+--
+-- Package: String related functions and types
+--
+-- Description:
+-- ------------------------------------
+-- For detailed documentation see below.
+--
+-- License:
+-- ============================================================================
+-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
+-- Chair for VLSI-Design, Diagnostics and Architecture
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use IEEE.math_real.all;
+
+library PoC;
+use PoC.config.all;
+use PoC.utils.all;
+--use PoC.FileIO.all;
+
+
+package strings is
+ -- default fill and string termination character for fixed size strings
+ -- ===========================================================================
+ constant C_POC_NUL : CHARACTER := ite((SYNTHESIS_TOOL /= SYNTHESIS_TOOL_ALTERA_QUARTUS2), NUL, '`');
+ -- character 0 causes Quartus to crash, if uses to pad STRINGs
+ -- characters < 32 (control characters) are not supported in Quartus
+ -- characters > 127 are not supported in VHDL files (strict ASCII files)
+ -- character 255 craches ISE log window (created by 'CHARACTER'val(255)')
+
+ -- Type declarations
+ -- ===========================================================================
+ subtype T_RAWCHAR is STD_LOGIC_VECTOR(7 downto 0);
+ type T_RAWSTRING is array (NATURAL range <>) of T_RAWCHAR;
+
+ -- testing area:
+ -- ===========================================================================
+ function to_IPStyle(str : STRING) return T_IPSTYLE;
+
+ -- to_char
+ function to_char(value : STD_LOGIC) return CHARACTER;
+ function to_char(value : NATURAL) return CHARACTER;
+ function to_char(rawchar : T_RAWCHAR) return CHARACTER;
+
+ -- chr_is* function
+ function chr_isDigit(chr : character) return boolean;
+ function chr_isLowerHexDigit(chr : character) return boolean;
+ function chr_isUpperHexDigit(chr : character) return boolean;
+ function chr_isHexDigit(chr : character) return boolean;
+ function chr_isLower(chr : character) return boolean;
+ function chr_isLowerAlpha(chr : character) return boolean;
+ function chr_isUpper(chr : character) return boolean;
+ function chr_isUpperAlpha(chr : character) return boolean;
+ function chr_isAlpha(chr : character) return boolean;
+
+ -- raw_format_* functions
+ function raw_format_bool_bin(value : BOOLEAN) return STRING;
+ function raw_format_bool_chr(value : BOOLEAN) return STRING;
+ function raw_format_bool_str(value : BOOLEAN) return STRING;
+ function raw_format_slv_bin(slv : STD_LOGIC_VECTOR) return STRING;
+ function raw_format_slv_oct(slv : STD_LOGIC_VECTOR) return STRING;
+ function raw_format_slv_dec(slv : STD_LOGIC_VECTOR) return STRING;
+ function raw_format_slv_hex(slv : STD_LOGIC_VECTOR) return STRING;
+ function raw_format_nat_bin(value : NATURAL) return STRING;
+ function raw_format_nat_oct(value : NATURAL) return STRING;
+ function raw_format_nat_dec(value : NATURAL) return STRING;
+ function raw_format_nat_hex(value : NATURAL) return STRING;
+
+ -- str_format_* functions
+ function str_format(value : REAL; precision : NATURAL := 3) return STRING;
+
+ -- to_string
+ function to_string(value : BOOLEAN) return STRING;
+ function to_string(value : INTEGER; base : POSITIVE := 10) return STRING;
+ function to_string(slv : STD_LOGIC_VECTOR; format : CHARACTER; length : NATURAL := 0; fill : CHARACTER := '0') return STRING;
+ function to_string(rawstring : T_RAWSTRING) return STRING;
+
+ -- to_slv
+ function to_slv(rawstring : T_RAWSTRING) return STD_LOGIC_VECTOR;
+
+ -- digit subtypes incl. error value (-1)
+ subtype T_DIGIT_BIN is INTEGER range -1 to 1;
+ subtype T_DIGIT_OCT is INTEGER range -1 to 7;
+ subtype T_DIGIT_DEC is INTEGER range -1 to 9;
+ subtype T_DIGIT_HEX is INTEGER range -1 to 15;
+
+ -- to_digit*
+ function to_digit_bin(chr : character) return T_DIGIT_BIN;
+ function to_digit_oct(chr : character) return T_DIGIT_OCT;
+ function to_digit_dec(chr : character) return T_DIGIT_DEC;
+ function to_digit_hex(chr : character) return T_DIGIT_HEX;
+ function to_digit(chr : character; base : character := 'd') return integer;
+
+ -- to_natural*
+ function to_natural_bin(str : STRING) return INTEGER;
+ function to_natural_oct(str : STRING) return INTEGER;
+ function to_natural_dec(str : STRING) return INTEGER;
+ function to_natural_hex(str : STRING) return INTEGER;
+ function to_natural(str : STRING; base : CHARACTER := 'd') return INTEGER;
+
+ -- to_raw*
+ function to_RawChar(char : character) return T_RAWCHAR;
+ function to_RawString(str : string) return T_RAWSTRING;
+
+ -- resize
+ function resize(str : STRING; size : POSITIVE; FillChar : CHARACTER := C_POC_NUL) return STRING;
+-- function resize(rawstr : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING;
+
+ -- Character functions
+ function chr_toLower(chr : character) return character;
+ function chr_toUpper(chr : character) return character;
+
+ -- String functions
+ function str_length(str : STRING) return NATURAL;
+ function str_equal(str1 : STRING; str2 : STRING) return BOOLEAN;
+ function str_match(str1 : STRING; str2 : STRING) return BOOLEAN;
+ function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN;
+ function str_pos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER;
+ function str_pos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER;
+ function str_ipos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER;
+ function str_ipos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER;
+ function str_find(str : STRING; chr : CHARACTER) return BOOLEAN;
+ function str_find(str : STRING; pattern : STRING) return BOOLEAN;
+ function str_ifind(str : STRING; chr : CHARACTER) return BOOLEAN;
+ function str_ifind(str : STRING; pattern : STRING) return BOOLEAN;
+ function str_replace(str : STRING; pattern : STRING; replace : STRING) return STRING;
+ function str_substr(str : STRING; start : INTEGER := 0; length : INTEGER := 0) return STRING;
+ function str_ltrim(str : STRING; char : CHARACTER := ' ') return STRING;
+ function str_rtrim(str : STRING; char : CHARACTER := ' ') return STRING;
+ function str_trim(str : STRING) return STRING;
+ function str_calign(str : STRING; length : NATURAL; FillChar : CHARACTER := ' ') return STRING;
+ function str_lalign(str : STRING; length : NATURAL; FillChar : CHARACTER := ' ') return STRING;
+ function str_ralign(str : STRING; length : NATURAL; FillChar : CHARACTER := ' ') return STRING;
+ function str_toLower(str : STRING) return STRING;
+ function str_toUpper(str : STRING) return STRING;
+
+end package;
+
+
+package body strings is
+
+ --
+ function to_IPStyle(str : STRING) return T_IPSTYLE is
+ begin
+ for i in T_IPSTYLE'pos(T_IPSTYLE'low) to T_IPSTYLE'pos(T_IPSTYLE'high) loop
+ if str_imatch(str, T_IPSTYLE'image(T_IPSTYLE'val(I))) then
+ return T_IPSTYLE'val(i);
+ end if;
+ end loop;
+
+ report "Unknown IPStyle: '" & str & "'" severity FAILURE;
+ end function;
+
+ -- to_char
+ -- ===========================================================================
+ function to_char(value : STD_LOGIC) return CHARACTER is
+ begin
+ case value IS
+ when 'U' => return 'U';
+ when 'X' => return 'X';
+ when '0' => return '0';
+ when '1' => return '1';
+ when 'Z' => return 'Z';
+ when 'W' => return 'W';
+ when 'L' => return 'L';
+ when 'H' => return 'H';
+ when '-' => return '-';
+ when others => return 'X';
+ end case;
+ end function;
+
+ -- TODO: rename to to_HexDigit(..) ?
+ function to_char(value : natural) return character is
+ constant HEX : string := "0123456789ABCDEF";
+ begin
+ return ite(value < 16, HEX(value+1), 'X');
+ end function;
+
+ function to_char(rawchar : T_RAWCHAR) return CHARACTER is
+ begin
+ return CHARACTER'val(to_integer(unsigned(rawchar)));
+ end function;
+
+ -- chr_is* function
+ function chr_isDigit(chr : character) return boolean is
+ begin
+ return (character'pos('0') <= character'pos(chr)) and (character'pos(chr) <= character'pos('9'));
+ end function;
+
+ function chr_isLowerHexDigit(chr : character) return boolean is
+ begin
+ return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('f'));
+ end function;
+
+ function chr_isUpperHexDigit(chr : character) return boolean is
+ begin
+ return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('F'));
+ end function;
+
+ function chr_isHexDigit(chr : character) return boolean is
+ begin
+ return chr_isDigit(chr) or chr_isLowerHexDigit(chr) or chr_isUpperHexDigit(chr);
+ end function;
+
+ function chr_isLower(chr : character) return boolean is
+ begin
+ return chr_isLowerAlpha(chr);
+ end function;
+
+ function chr_isLowerAlpha(chr : character) return boolean is
+ begin
+ return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('z'));
+ end function;
+
+ function chr_isUpper(chr : character) return boolean is
+ begin
+ return chr_isUpperAlpha(chr);
+ end function;
+
+ function chr_isUpperAlpha(chr : character) return boolean is
+ begin
+ return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('Z'));
+ end function;
+
+ function chr_isAlpha(chr : character) return boolean is
+ begin
+ return chr_isLowerAlpha(chr) or chr_isUpperAlpha(chr);
+ end function;
+
+ -- raw_format_* functions
+ -- ===========================================================================
+ function raw_format_bool_bin(value : BOOLEAN) return STRING is
+ begin
+ return ite(value, "1", "0");
+ end function;
+
+ function raw_format_bool_chr(value : BOOLEAN) return STRING is
+ begin
+ return ite(value, "T", "F");
+ end function;
+
+ function raw_format_bool_str(value : BOOLEAN) return STRING is
+ begin
+ return str_toUpper(boolean'image(value));
+ end function;
+
+ function raw_format_slv_bin(slv : STD_LOGIC_VECTOR) return STRING is
+ variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
+ variable Result : STRING(1 to slv'length);
+ variable j : NATURAL;
+ begin
+ -- convert input slv to a downto ranged vector and normalize range to slv'low = 0
+ Value := movez(ite(slv'ascending, descend(slv), slv));
+
+ -- convert each bit to a character
+ J := 0;
+ for i in Result'reverse_range loop
+ Result(i) := to_char(Value(j));
+ j := j + 1;
+ end loop;
+
+ return Result;
+ end function;
+
+ function raw_format_slv_oct(slv : STD_LOGIC_VECTOR) return STRING is
+ variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
+ variable Digit : STD_LOGIC_VECTOR(2 downto 0);
+ variable Result : STRING(1 to div_ceil(slv'length, 3));
+ variable j : NATURAL;
+ begin
+ -- convert input slv to a downto ranged vector; normalize range to slv'low = 0 and resize it to a multiple of 3
+ Value := resize(movez(ite(slv'ascending, descend(slv), slv)), (Result'length * 3));
+
+ -- convert 3 bit to a character
+ j := 0;
+ for i in Result'reverse_range loop
+ Digit := Value((j * 3) + 2 downto (j * 3));
+ Result(i) := to_char(to_integer(unsigned(Digit)));
+ j := j + 1;
+ end loop;
+
+ return Result;
+ end function;
+
+ function raw_format_slv_dec(slv : STD_LOGIC_VECTOR) return STRING is
+ variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
+ variable Result : STRING(1 to div_ceil(slv'length, 3));
+
+ subtype TT_BCD is INTEGER range 0 to 31;
+ type TT_BCD_VECTOR is array(natural range <>) of TT_BCD;
+
+ variable Temp : TT_BCD_VECTOR(div_ceil(slv'length, 3) - 1 downto 0);
+ variable Carry : T_UINT_8;
+
+ variable Pos : NATURAL;
+ begin
+ Temp := (others => 0);
+ Pos := 0;
+
+ -- convert input slv to a downto ranged vector
+ Value := ite(slv'ascending, descend(slv), slv);
+
+ for i in Value'range loop
+ Carry := to_int(Value(i));
+ for j in Temp'reverse_range loop
+ Temp(j) := Temp(j) * 2 + Carry;
+ Carry := to_int(Temp(j) > 9);
+ Temp(j) := Temp(j) - to_int((Temp(j) > 9), 0, 10);
+ end loop;
+ end loop;
+
+ for i in Result'range loop
+ Result(i) := to_char(Temp(Temp'high - i + 1));
+ if ((Result(i) /= '0') and (Pos = 0)) then
+ Pos := i;
+ end if;
+ end loop;
+
+ -- trim leading zeros, except the last
+ return Result(imin(Pos, Result'high) to Result'high);
+ end function;
+
+ function raw_format_slv_hex(slv : STD_LOGIC_VECTOR) return STRING is
+ variable Value : STD_LOGIC_VECTOR(4*div_ceil(slv'length, 4) - 1 downto 0);
+ variable Digit : STD_LOGIC_VECTOR(3 downto 0);
+ variable Result : STRING(1 to div_ceil(slv'length, 4));
+ variable j : NATURAL;
+ begin
+ Value := resize(slv, Value'length);
+ j := 0;
+ for i in Result'reverse_range loop
+ Digit := Value((j * 4) + 3 downto (j * 4));
+ Result(i) := to_char(to_integer(unsigned(Digit)));
+ j := j + 1;
+ end loop;
+
+ return Result;
+ end function;
+
+ function raw_format_nat_bin(value : NATURAL) return STRING is
+ begin
+ return raw_format_slv_bin(to_slv(value, log2ceilnz(value+1)));
+ end function;
+
+ function raw_format_nat_oct(value : NATURAL) return STRING is
+ begin
+ return raw_format_slv_oct(to_slv(value, log2ceilnz(value+1)));
+ end function;
+
+ function raw_format_nat_dec(value : NATURAL) return STRING is
+ begin
+ return INTEGER'image(value);
+ end function;
+
+ function raw_format_nat_hex(value : NATURAL) return STRING is
+ begin
+ return raw_format_slv_hex(to_slv(value, log2ceilnz(value+1)));
+ end function;
+
+ -- str_format_* functions
+ -- ===========================================================================
+ function str_format(value : REAL; precision : NATURAL := 3) return STRING is
+ constant s : REAL := sign(value);
+ constant val : REAL := value * s;
+ constant int : INTEGER := integer(floor(val));
+ constant frac : INTEGER := integer(round((val - real(int)) * 10.0**precision));
+ constant overflow : boolean := frac >= 10**precision;
+ constant int2 : INTEGER := ite(overflow, int+1, int);
+ constant frac2 : INTEGER := ite(overflow, frac-10**precision, frac);
+ constant frac_str : STRING := INTEGER'image(frac2);
+ constant res : STRING := INTEGER'image(int2) & "." & (2 to (precision - frac_str'length + 1) => '0') & frac_str;
+ begin
+ return ite ((s < 0.0), "-" & res, res);
+ end function;
+
+ -- to_string
+ -- ===========================================================================
+ function to_string(value : boolean) return string is
+ begin
+ return raw_format_bool_str(value);
+ end function;
+
+ function to_string(value : INTEGER; base : POSITIVE := 10) return STRING is
+ constant absValue : NATURAL := abs(value);
+ constant len : POSITIVE := log10ceilnz(absValue);
+ variable power : POSITIVE;
+ variable Result : STRING(1 TO len);
+
+ begin
+ power := 1;
+
+ if (base = 10) then
+ return INTEGER'image(value);
+ else
+ for i in len downto 1 loop
+ Result(i) := to_char(absValue / power MOD base);
+ power := power * base;
+ end loop;
+
+ if (value < 0) then
+ return '-' & Result;
+ else
+ return Result;
+ end if;
+ end if;
+ end function;
+
+ -- TODO: rename to slv_format(..) ?
+ function to_string(slv : STD_LOGIC_VECTOR; format : CHARACTER; length : NATURAL := 0; fill : CHARACTER := '0') return STRING is
+ constant int : INTEGER := ite((slv'length <= 31), to_integer(unsigned(resize(slv, 31))), 0);
+ constant str : STRING := INTEGER'image(int);
+ constant bin_len : POSITIVE := slv'length;
+ constant dec_len : POSITIVE := str'length;--log10ceilnz(int);
+ constant hex_len : POSITIVE := ite(((bin_len MOD 4) = 0), (bin_len / 4), (bin_len / 4) + 1);
+ constant len : NATURAL := ite((format = 'b'), bin_len,
+ ite((format = 'd'), dec_len,
+ ite((format = 'h'), hex_len, 0)));
+ variable j : NATURAL;
+ variable Result : STRING(1 to ite((length = 0), len, imax(len, length)));
+ begin
+ j := 0;
+ Result := (others => fill);
+
+ if (format = 'b') then
+ for i in Result'reverse_range loop
+ Result(i) := to_char(slv(j));
+ j := j + 1;
+ end loop;
+ elsif (format = 'd') then
+-- if (slv'length < 32) then
+-- return INTEGER'image(int);
+-- else
+-- return raw_format_slv_dec(slv);
+-- end if;
+ Result(Result'length - str'length + 1 to Result'high) := str;
+ elsif (format = 'h') then
+ for i in Result'reverse_range loop
+ Result(i) := to_char(to_integer(unsigned(slv((j * 4) + 3 downto (j * 4)))));
+ j := j + 1;
+ end loop;
+ else
+ report "unknown format" severity FAILURE;
+ end if;
+
+ return Result;
+ end function;
+
+ function to_string(rawstring : T_RAWSTRING) return STRING is
+ variable str : STRING(1 to rawstring'length);
+ begin
+ for i in rawstring'low to rawstring'high loop
+ str(I - rawstring'low + 1) := to_char(rawstring(I));
+ end loop;
+
+ return str;
+ end function;
+
+ -- to_slv
+ -- ===========================================================================
+ function to_slv(rawstring : T_RAWSTRING) return STD_LOGIC_VECTOR is
+ variable result : STD_LOGIC_VECTOR((rawstring'length * 8) - 1 downto 0);
+ begin
+ for i in rawstring'range loop
+ result(((i - rawstring'low) * 8) + 7 downto (i - rawstring'low) * 8) := rawstring(i);
+ end loop;
+ return result;
+ end function;
+
+ -- to_*
+ -- ===========================================================================
+ function to_digit_bin(chr : character) return T_DIGIT_BIN is
+ begin
+ case chr is
+ when '0' => return 0;
+ when '1' => return 1;
+ when others => return -1;
+ end case;
+ end function;
+
+ function to_digit_oct(chr : character) return T_DIGIT_OCT is
+ variable dec : integer;
+ begin
+ dec := to_digit_dec(chr);
+ return ite((dec < 8), dec, -1);
+ end function;
+
+ function to_digit_dec(chr : character) return T_DIGIT_DEC is
+ begin
+ if chr_isDigit(chr) then
+ return character'pos(chr) - character'pos('0');
+ else
+ return -1;
+ end if;
+ end function;
+
+ function to_digit_hex(chr : character) return T_DIGIT_HEX is
+ begin
+ if chr_isDigit(chr) then return character'pos(chr) - character'pos('0');
+ elsif chr_isLowerHexDigit(chr) then return character'pos(chr) - character'pos('a') + 10;
+ elsif chr_isUpperHexDigit(chr) then return character'pos(chr) - character'pos('A') + 10;
+ else return -1;
+ end if;
+ end function;
+
+ function to_digit(chr : character; base : character := 'd') return integer is
+ begin
+ case base is
+ when 'b' => return to_digit_bin(chr);
+ when 'o' => return to_digit_oct(chr);
+ when 'd' => return to_digit_dec(chr);
+ when 'h' => return to_digit_hex(chr);
+ when others => report "Unknown base character: " & base & "." severity failure;
+ -- return statement is explicitly missing otherwise XST won't stop
+ end case;
+ end function;
+
+ function to_natural_bin(str : STRING) return INTEGER is
+ variable Result : NATURAL;
+ variable Digit : INTEGER;
+ begin
+ for i in str'range loop
+ Digit := to_digit_bin(str(I));
+ if (Digit /= -1) then
+ Result := Result * 2 + Digit;
+ else
+ return -1;
+ end if;
+ end loop;
+
+ return Result;
+ end function;
+
+ function to_natural_oct(str : STRING) return INTEGER is
+ variable Result : NATURAL;
+ variable Digit : INTEGER;
+ begin
+ for i in str'range loop
+ Digit := to_digit_oct(str(I));
+ if (Digit /= -1) then
+ Result := Result * 8 + Digit;
+ else
+ return -1;
+ end if;
+ end loop;
+
+ return Result;
+ end function;
+
+ function to_natural_dec(str : STRING) return INTEGER is
+ variable Result : NATURAL;
+ variable Digit : INTEGER;
+ begin
+ for i in str'range loop
+ Digit := to_digit_dec(str(I));
+ if (Digit /= -1) then
+ Result := Result * 10 + Digit;
+ else
+ return -1;
+ end if;
+ end loop;
+
+ return Result;
+-- return INTEGER'value(str); -- 'value(...) is not supported by Vivado Synth 2014.1
+ end function;
+
+ function to_natural_hex(str : STRING) return INTEGER is
+ variable Result : NATURAL;
+ variable Digit : INTEGER;
+ begin
+ for i in str'range loop
+ Digit := to_digit_hex(str(I));
+ if (Digit /= -1) then
+ Result := Result * 16 + Digit;
+ else
+ return -1;
+ end if;
+ end loop;
+
+ return Result;
+ end function;
+
+ function to_natural(str : STRING; base : CHARACTER := 'd') return INTEGER is
+ begin
+ case base is
+ when 'b' => return to_natural_bin(str);
+ when 'o' => return to_natural_oct(str);
+ when 'd' => return to_natural_dec(str);
+ when 'h' => return to_natural_hex(str);
+ when others => report "unknown base" severity ERROR;
+ end case;
+ end function;
+
+ -- to_raw*
+ -- ===========================================================================
+ function to_RawChar(char : character) return t_rawchar is
+ begin
+ return std_logic_vector(to_unsigned(character'pos(char), t_rawchar'length));
+ end function;
+
+ function to_RawString(str : STRING) return T_RAWSTRING is
+ variable rawstr : T_RAWSTRING(0 to str'length - 1);
+ begin
+ for i in str'low to str'high loop
+ rawstr(i - str'low) := to_RawChar(str(i));
+ end loop;
+ return rawstr;
+ end function;
+
+ -- resize
+ -- ===========================================================================
+ function resize(str : STRING; size : POSITIVE; FillChar : CHARACTER := C_POC_NUL) return STRING is
+ constant ConstNUL : STRING(1 to 1) := (others => C_POC_NUL);
+ variable Result : STRING(1 to size);
+ begin
+ Result := (others => FillChar);
+ if (str'length > 0) then -- workaround for Quartus II
+ Result(1 to imin(size, imax(1, str'length))) := ite((str'length > 0), str(1 to imin(size, str'length)), ConstNUL);
+ end if;
+ return Result;
+ end function;
+
+-- function resize(str : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING is
+-- constant ConstNUL : T_RAWSTRING(1 to 1) := (others => x"00");
+-- variable Result : T_RAWSTRING(1 to size);
+-- function ifthenelse(cond : BOOLEAN; value1 : T_RAWSTRING; value2 : T_RAWSTRING) return T_RAWSTRING is
+-- begin
+-- if cond then
+-- return value1;
+-- else
+-- return value2;
+-- end if;
+-- end function;
+-- begin
+-- Result := (others => FillChar);
+-- if (str'length > 0) then
+-- Result(1 to imin(size, imax(1, str'length))) := ifthenelse((str'length > 0), str(1 to imin(size, str'length)), ConstNUL);
+-- end if;
+-- return Result;
+-- end function;
+
+
+ -- Character functions
+ -- ===========================================================================
+ function chr_toLower(chr : character) return character is
+ begin
+ if chr_isUpperAlpha(chr) then
+ return character'val(character'pos(chr) - character'pos('A') + character'pos('a'));
+ else
+ return chr;
+ end if;
+ end function;
+
+ function chr_toUpper(chr : character) return character is
+ begin
+ if chr_isLowerAlpha(chr) then
+ return character'val(character'pos(chr) - character'pos('a') + character'pos('A'));
+ else
+ return chr;
+ end if;
+ end function;
+
+ -- String functions
+ -- ===========================================================================
+ function str_length(str : STRING) return NATURAL is
+ begin
+ for i in str'range loop
+ if (str(i) = C_POC_NUL) then
+ return i - str'low;
+ end if;
+ end loop;
+ return str'length;
+ end function;
+
+ function str_equal(str1 : STRING; str2 : STRING) return BOOLEAN is
+ begin
+ if str1'length /= str2'length then
+ return FALSE;
+ else
+ return (str1 = str2);
+ end if;
+ end function;
+
+ function str_match(str1 : STRING; str2 : STRING) return BOOLEAN is
+ constant len : NATURAL := imin(str1'length, str2'length);
+ begin
+ -- if both strings are empty
+ if ((str1'length = 0 ) and (str2'length = 0)) then return TRUE; end if;
+ -- compare char by char
+ for i in str1'low to str1'low + len - 1 loop
+ if (str1(i) /= str2(str2'low + (i - str1'low))) then
+ return FALSE;
+ elsif ((str1(i) = C_POC_NUL) xor (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then
+ return FALSE;
+ elsif ((str1(i) = C_POC_NUL) and (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then
+ return TRUE;
+ end if;
+ end loop;
+ -- check special cases,
+ return (((str1'length = len) and (str2'length = len)) or -- both strings are fully consumed and equal
+ ((str1'length > len) and (str1(str1'low + len) = C_POC_NUL)) or -- str1 is longer, but str_length equals len
+ ((str2'length > len) and (str2(str2'low + len) = C_POC_NUL))); -- str2 is longer, but str_length equals len
+ end function;
+
+ function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN is
+ begin
+ return str_match(str_toLower(str1), str_toLower(str2));
+ end function;
+
+ function str_pos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER is
+ begin
+ for i in imax(str'low, start) to str'high loop
+ exit when (str(i) = C_POC_NUL);
+ if (str(i) = chr) then
+ return i;
+ end if;
+ end loop;
+ return -1;
+ end function;
+
+ function str_pos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER is
+ begin
+ for i in imax(str'low, start) to (str'high - pattern'length + 1) loop
+ exit when (str(i) = C_POC_NUL);
+ if (str(i to i + pattern'length - 1) = pattern) then
+ return i;
+ end if;
+ end loop;
+ return -1;
+ end function;
+
+ function str_ipos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER is
+ begin
+ return str_pos(str_toLower(str), chr_toLower(chr));
+ end function;
+
+ function str_ipos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER is
+ begin
+ return str_pos(str_toLower(str), str_toLower(pattern));
+ end function;
+
+-- function str_pos(str1 : STRING; str2 : STRING) return INTEGER is
+-- variable PrefixTable : T_INTVEC(0 to str2'length);
+-- variable j : INTEGER;
+-- begin
+-- -- construct prefix table for KMP algorithm
+-- j := -1;
+-- PrefixTable(0) := -1;
+-- for i in str2'range loop
+-- while ((j >= 0) and str2(j + 1) /= str2(i)) loop
+-- j := PrefixTable(j);
+-- end loop;
+--
+-- j := j + 1;
+-- PrefixTable(i - 1) := j + 1;
+-- end loop;
+--
+-- -- search pattern str2 in text str1
+-- j := 0;
+-- for i in str1'range loop
+-- while ((j >= 0) and str1(i) /= str2(j + 1)) loop
+-- j := PrefixTable(j);
+-- end loop;
+--
+-- j := j + 1;
+-- if ((j + 1) = str2'high) then
+-- return i - str2'length + 1;
+-- end if;
+-- end loop;
+--
+-- return -1;
+-- end function;
+
+ function str_find(str : STRING; chr : CHARACTER) return boolean is
+ begin
+ return (str_pos(str, chr) > 0);
+ end function;
+
+ function str_find(str : STRING; pattern : STRING) return boolean is
+ begin
+ return (str_pos(str, pattern) > 0);
+ end function;
+
+ function str_ifind(str : STRING; chr : CHARACTER) return boolean is
+ begin
+ return (str_ipos(str, chr) > 0);
+ end function;
+
+ function str_ifind(str : STRING; pattern : STRING) return boolean is
+ begin
+ return (str_ipos(str, pattern) > 0);
+ end function;
+
+ function str_replace(str : STRING; pattern : STRING; replace : STRING) return STRING is
+ variable pos : INTEGER;
+ begin
+ pos := str_pos(str, pattern);
+ if (pos > 0) then
+ if (pos = 1) then
+ return replace & str(pattern'length + 1 to str'length);
+ elsif (pos = str'length - pattern'length + 1) then
+ return str(1 to str'length - pattern'length) & replace;
+ else
+ return str(1 to pos - 1) & replace & str(pos + pattern'length to str'length);
+ end if;
+ else
+ return str;
+ end if;
+ end function;
+
+ -- examples:
+ -- 123456789ABC
+ -- input string: "Hello World."
+ -- low=1; high=12; length=12
+ --
+ -- str_substr("Hello World.", 0, 0) => "Hello World." - copy all
+ -- str_substr("Hello World.", 7, 0) => "World." - copy from pos 7 to end of string
+ -- str_substr("Hello World.", 7, 5) => "World" - copy from pos 7 for 5 characters
+ -- str_substr("Hello World.", 0, -7) => "Hello World." - copy all until character 8 from right boundary
+ function str_substr(str : STRING; start : INTEGER := 0; length : INTEGER := 0) return STRING is
+ variable StartOfString : positive;
+ variable EndOfString : positive;
+ begin
+ if (start < 0) then -- start is negative -> start substring at right string boundary
+ StartOfString := str'high + start + 1;
+ elsif (start = 0) then -- start is zero -> start substring at left string boundary
+ StartOfString := str'low;
+ else -- start is positive -> start substring at left string boundary + offset
+ StartOfString := start;
+ end if;
+
+ if (length < 0) then -- length is negative -> end substring at length'th character before right string boundary
+ EndOfString := str'high + length;
+ elsif (length = 0) then -- length is zero -> end substring at right string boundary
+ EndOfString := str'high;
+ else -- length is positive -> end substring at StartOfString + length
+ EndOfString := StartOfString + length - 1;
+ end if;
+
+ if (StartOfString < str'low) then report "StartOfString is out of str's range. (str=" & str & ")" severity error; end if;
+ if (EndOfString < str'high) then report "EndOfString is out of str's range. (str=" & str & ")" severity error; end if;
+
+ return str(StartOfString to EndOfString);
+ end function;
+
+ function str_ltrim(str : STRING; char : CHARACTER := ' ') return STRING is
+ begin
+ for i in str'range loop
+ if (str(i) /= char) then
+ return str(i to str'high);
+ end if;
+ end loop;
+ return "";
+ end function;
+
+ function str_rtrim(str : STRING; char : CHARACTER := ' ') return STRING is
+ begin
+ for i in str'reverse_range loop
+ if (str(i) /= char) then
+ return str(str'low to i);
+ end if;
+ end loop;
+ return "";
+ end function;
+
+ function str_trim(str : STRING) return STRING is
+ begin
+ return str(str'low to str'low + str_length(str) - 1);
+ end function;
+
+ function str_calign(str : STRING; length : NATURAL; FillChar : CHARACTER := ' ') return STRING is
+ constant Start : POSITIVE := (length - str'length) / 2;
+ variable Result : STRING(1 to length);
+ begin
+ Result := (others => FillChar);
+ Result(Start to (Start + str'length)) := str;
+ return Result;
+ end function;
+
+ function str_lalign(str : STRING; length : NATURAL; FillChar : CHARACTER := ' ') return STRING is
+ variable Result : STRING(1 to length);
+ begin
+ Result := (others => FillChar);
+ Result(1 to str'length) := str;
+ return Result;
+ end function;
+
+ function str_ralign(str : STRING; length : NATURAL; FillChar : CHARACTER := ' ') return STRING is
+ variable Result : STRING(1 to length);
+ begin
+ Result := (others => FillChar);
+ Result((length - str'length + 1) to length) := str;
+ return Result;
+ end function;
+
+ function str_toLower(str : STRING) return STRING is
+ variable temp : STRING(str'range);
+ begin
+ for i in str'range loop
+ temp(I) := chr_toLower(str(I));
+ end loop;
+ return temp;
+ end function;
+
+ function str_toUpper(str : STRING) return STRING is
+ variable temp : STRING(str'range);
+ begin
+ for i in str'range loop
+ temp(I) := chr_toUpper(str(I));
+ end loop;
+ return temp;
+ end function;
+
+end package body;
diff --git a/testsuite/gna/bug037/testsuite.sh b/testsuite/gna/bug037/testsuite.sh index ea3e4df33..4b6af06b6 100755 --- a/testsuite/gna/bug037/testsuite.sh +++ b/testsuite/gna/bug037/testsuite.sh @@ -7,4 +7,26 @@ elab_simulate repro --dump-rti clean +GHDL_STD_FLAGS=--std=08 + +analyze --work=poc my_config_ML505.vhdl +analyze --work=poc my_project.vhdl +analyze --work=poc utils.vhdl +analyze --work=poc config.vhdl +analyze --work=poc strings.vhdl +analyze --work=poc vectors.vhdl +analyze --work=poc physical.vhdl +analyze --work=poc sim_types.vhdl +analyze --work=poc sim_protected.v08.vhdl +analyze --work=poc sim_global.v08.vhdl +analyze --work=poc sim_simulation.v08.vhdl + +analyze --work=poc arith.pkg.vhdl +analyze --work=poc arith_addw.vhdl +analyze arith_addw_tb.vhdl +elab_simulate arith_addw_tb --stop-time=100ns # --wave=arith.ghw + +clean +clean poc + echo "Test successful" diff --git a/testsuite/gna/bug037/utils.vhdl b/testsuite/gna/bug037/utils.vhdl new file mode 100644 index 000000000..89dcc1fef --- /dev/null +++ b/testsuite/gna/bug037/utils.vhdl @@ -0,0 +1,987 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+--
+-- ============================================================================
+-- Package: Common functions and types
+--
+-- Authors: Thomas B. Preusser
+-- Martin Zabel
+-- Patrick Lehmann
+--
+-- Description:
+-- ------------------------------------
+-- For detailed documentation see below.
+--
+-- License:
+-- ============================================================================
+-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
+-- Chair for VLSI-Design, Diagnostics and Architecture
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- ============================================================================
+
+library IEEE;
+
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use IEEE.math_real.all;
+
+library PoC;
+use PoC.my_config.all;
+
+
+package utils is
+ -- PoC settings
+ -- ==========================================================================
+ constant POC_VERBOSE : BOOLEAN := MY_VERBOSE;
+
+ -- Environment
+ -- ==========================================================================
+ -- Distinguishes simulation from synthesis
+ constant SIMULATION : BOOLEAN; -- deferred constant declaration
+
+ -- Type declarations
+ -- ==========================================================================
+
+ --+ Vectors of primitive standard types +++++++++++++++++++++++++++++++++++++
+ type T_BOOLVEC is array(NATURAL range <>) of BOOLEAN;
+ type T_INTVEC is array(NATURAL range <>) of INTEGER;
+ type T_NATVEC is array(NATURAL range <>) of NATURAL;
+ type T_POSVEC is array(NATURAL range <>) of POSITIVE;
+ type T_REALVEC is array(NATURAL range <>) of REAL;
+
+ --+ Integer subranges sometimes useful for speeding up simulation ++++++++++
+ subtype T_INT_8 is INTEGER range -128 to 127;
+ subtype T_INT_16 is INTEGER range -32768 to 32767;
+ subtype T_UINT_8 is INTEGER range 0 to 255;
+ subtype T_UINT_16 is INTEGER range 0 to 65535;
+
+ --+ Enums ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ -- Intellectual Property (IP) type
+ type T_IPSTYLE is (IPSTYLE_HARD, IPSTYLE_SOFT);
+
+ -- Bit Order
+ type T_BIT_ORDER is (LSB_FIRST, MSB_FIRST);
+
+ -- Byte Order (Endian)
+ type T_BYTE_ORDER is (LITTLE_ENDIAN, BIG_ENDIAN);
+
+ -- rounding style
+ type T_ROUNDING_STYLE is (ROUND_TO_NEAREST, ROUND_TO_ZERO, ROUND_TO_INF, ROUND_UP, ROUND_DOWN);
+
+ type T_BCD is array(3 downto 0) of std_logic;
+ type T_BCD_VECTOR is array(NATURAL range <>) of T_BCD;
+ constant C_BCD_MINUS : T_BCD := "1010";
+ constant C_BCD_OFF : T_BCD := "1011";
+
+
+ -- Function declarations
+ -- ==========================================================================
+
+ --+ Division ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ -- Calculates: ceil(a / b)
+ function div_ceil(a : NATURAL; b : POSITIVE) return NATURAL;
+
+ --+ Power +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ -- is input a power of 2?
+ function is_pow2(int : NATURAL) return BOOLEAN;
+ -- round to next power of 2
+ function ceil_pow2(int : NATURAL) return POSITIVE;
+ -- round to previous power of 2
+ function floor_pow2(int : NATURAL) return NATURAL;
+
+ --+ Logarithm ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ -- Calculates: ceil(ld(arg))
+ function log2ceil(arg : positive) return natural;
+ -- Calculates: max(1, ceil(ld(arg)))
+ function log2ceilnz(arg : positive) return positive;
+ -- Calculates: ceil(lg(arg))
+ function log10ceil(arg : POSITIVE) return NATURAL;
+ -- Calculates: max(1, ceil(lg(arg)))
+ function log10ceilnz(arg : POSITIVE) return POSITIVE;
+
+ --+ if-then-else (ite) +++++++++++++++++++++++++++++++++++++++++++++++++++++
+ function ite(cond : BOOLEAN; value1 : BOOLEAN; value2 : BOOLEAN) return BOOLEAN;
+ function ite(cond : BOOLEAN; value1 : INTEGER; value2 : INTEGER) return INTEGER;
+ function ite(cond : BOOLEAN; value1 : REAL; value2 : REAL) return REAL;
+ function ite(cond : BOOLEAN; value1 : STD_LOGIC; value2 : STD_LOGIC) return STD_LOGIC;
+ function ite(cond : BOOLEAN; value1 : STD_LOGIC_VECTOR; value2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
+ function ite(cond : BOOLEAN; value1 : BIT_VECTOR; value2 : BIT_VECTOR) return BIT_VECTOR;
+ function ite(cond : BOOLEAN; value1 : UNSIGNED; value2 : UNSIGNED) return UNSIGNED;
+ function ite(cond : BOOLEAN; value1 : CHARACTER; value2 : CHARACTER) return CHARACTER;
+ function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING;
+
+ --+ Max / Min / Sum ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ function imin(arg1 : integer; arg2 : integer) return integer; -- Calculates: min(arg1, arg2) for integers
+ alias rmin is IEEE.math_real.realmin[real, real return real];
+ -- function rmin(arg1 : real; arg2 : real) return real; -- Calculates: min(arg1, arg2) for reals
+
+ function imin(vec : T_INTVEC) return INTEGER; -- Calculates: min(vec) for a integer vector
+ function imin(vec : T_NATVEC) return NATURAL; -- Calculates: min(vec) for a natural vector
+ function imin(vec : T_POSVEC) return POSITIVE; -- Calculates: min(vec) for a positive vector
+ function rmin(vec : T_REALVEC) return real; -- Calculates: min(vec) of real vector
+
+ function imax(arg1 : integer; arg2 : integer) return integer; -- Calculates: max(arg1, arg2) for integers
+ alias rmax is IEEE.math_real.realmax[real, real return real];
+ -- function rmax(arg1 : real; arg2 : real) return real; -- Calculates: max(arg1, arg2) for reals
+
+ function imax(vec : T_INTVEC) return INTEGER; -- Calculates: max(vec) for a integer vector
+ function imax(vec : T_NATVEC) return NATURAL; -- Calculates: max(vec) for a natural vector
+ function imax(vec : T_POSVEC) return POSITIVE; -- Calculates: max(vec) for a positive vector
+ function rmax(vec : T_REALVEC) return real; -- Calculates: max(vec) of real vector
+
+ function isum(vec : T_NATVEC) return NATURAL; -- Calculates: sum(vec) for a natural vector
+ function isum(vec : T_POSVEC) return natural; -- Calculates: sum(vec) for a positive vector
+ function isum(vec : T_INTVEC) return integer; -- Calculates: sum(vec) of integer vector
+ function rsum(vec : T_REALVEC) return real; -- Calculates: sum(vec) of real vector
+
+ --+ Conversions ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+ -- to integer: to_int
+ function to_int(bool : BOOLEAN; zero : INTEGER := 0; one : INTEGER := 1) return INTEGER;
+ function to_int(sl : STD_LOGIC; zero : INTEGER := 0; one : INTEGER := 1) return INTEGER;
+
+ -- to std_logic: to_sl
+ function to_sl(Value : BOOLEAN) return STD_LOGIC;
+ function to_sl(Value : CHARACTER) return STD_LOGIC;
+
+ -- to std_logic_vector: to_slv
+ function to_slv(Value : NATURAL; Size : POSITIVE) return STD_LOGIC_VECTOR; -- short for std_logic_vector(to_unsigned(Value, Size))
+
+ -- TODO: comment
+ function to_index(slv : UNSIGNED; max : NATURAL := 0) return INTEGER;
+ function to_index(slv : STD_LOGIC_VECTOR; max : NATURAL := 0) return INTEGER;
+
+ -- is_*
+ function is_sl(c : CHARACTER) return BOOLEAN;
+
+ --+ Basic Vector Utilities +++++++++++++++++++++++++++++++++++++++++++++++++
+
+ -- Aggregate functions
+ function slv_or (vec : STD_LOGIC_VECTOR) return STD_LOGIC;
+ function slv_nor (vec : STD_LOGIC_VECTOR) return STD_LOGIC;
+ function slv_and (vec : STD_LOGIC_VECTOR) return STD_LOGIC;
+ function slv_nand(vec : STD_LOGIC_VECTOR) return STD_LOGIC;
+ function slv_xor (vec : std_logic_vector) return std_logic;
+ -- NO slv_xnor! This operation would not be well-defined as
+ -- not xor(vec) /= vec_{n-1} xnor ... xnor vec_1 xnor vec_0 iff n is odd.
+
+ -- Reverses the elements of the passed Vector.
+ --
+ -- @synthesis supported
+ --
+ function reverse(vec : std_logic_vector) return std_logic_vector;
+ function reverse(vec : bit_vector) return bit_vector;
+ function reverse(vec : unsigned) return unsigned;
+
+ -- scale a value into a range [Minimum, Maximum]
+ function scale(Value : INTEGER; Minimum : INTEGER; Maximum : INTEGER; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
+ function scale(Value : REAL; Minimum : INTEGER; Maximum : INTEGER; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
+ function scale(Value : REAL; Minimum : REAL; Maximum : REAL) return REAL;
+
+ -- Resizes the vector to the specified length. The adjustment is make on
+ -- on the 'high end of the vector. The 'low index remains as in the argument.
+ -- If the result vector is larger, the extension uses the provided fill value
+ -- (default: '0').
+ -- Use the resize functions of the numeric_std package for value-preserving
+ -- resizes of the signed and unsigned data types.
+ --
+ -- @synthesis supported
+ --
+ function resize(vec : bit_vector; length : natural; fill : bit := '0')
+ return bit_vector;
+ function resize(vec : std_logic_vector; length : natural; fill : std_logic := '0')
+ return std_logic_vector;
+
+ -- Shift the index range of a vector by the specified offset.
+ function move(vec : std_logic_vector; ofs : integer) return std_logic_vector;
+
+ -- Shift the index range of a vector making vec'low = 0.
+ function movez(vec : std_logic_vector) return std_logic_vector;
+
+ function ascend(vec : std_logic_vector) return std_logic_vector;
+ function descend(vec : std_logic_vector) return std_logic_vector;
+
+ -- Least-Significant Set Bit (lssb):
+ -- Computes a vector of the same length as the argument with
+ -- at most one bit set at the rightmost '1' found in arg.
+ --
+ -- @synthesis supported
+ --
+ function lssb(arg : std_logic_vector) return std_logic_vector;
+ function lssb(arg : bit_vector) return bit_vector;
+
+ -- Returns the index of the least-significant set bit.
+ --
+ -- @synthesis supported
+ --
+ function lssb_idx(arg : std_logic_vector) return integer;
+ function lssb_idx(arg : bit_vector) return integer;
+
+ -- Most-Significant Set Bit (mssb): computes a vector of the same length
+ -- with at most one bit set at the leftmost '1' found in arg.
+ function mssb(arg : std_logic_vector) return std_logic_vector;
+ function mssb(arg : bit_vector) return bit_vector;
+ function mssb_idx(arg : std_logic_vector) return integer;
+ function mssb_idx(arg : bit_vector) return integer;
+
+ -- Swap sub vectors in vector (endian reversal)
+ function swap(slv : STD_LOGIC_VECTOR; Size : POSITIVE) return STD_LOGIC_VECTOR;
+
+ -- generate bit masks
+ function genmask_high(Bits : NATURAL; MaskLength : POSITIVE) return STD_LOGIC_VECTOR;
+ function genmask_low(Bits : NATURAL; MaskLength : POSITIVE) return STD_LOGIC_VECTOR;
+
+ --+ Encodings ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+ -- One-Hot-Code to Binary-Code.
+ function onehot2bin(onehot : std_logic_vector) return unsigned;
+
+ -- Converts Gray-Code into Binary-Code.
+ --
+ -- @synthesis supported
+ --
+ function gray2bin (gray_val : std_logic_vector) return std_logic_vector;
+
+ -- Binary-Code to One-Hot-Code
+ function bin2onehot(value : std_logic_vector) return std_logic_vector;
+
+ -- Binary-Code to Gray-Code
+ function bin2gray(value : std_logic_vector) return std_logic_vector;
+
+end package;
+
+
+package body utils is
+
+ -- Environment
+ -- ==========================================================================
+ function is_simulation return boolean is
+ variable ret : boolean;
+ begin
+ ret := false;
+ --synthesis translate_off
+ if Is_X('X') then ret := true; end if;
+ --synthesis translate_on
+ return ret;
+ end function;
+
+ -- deferred constant assignment
+ constant SIMULATION : BOOLEAN := is_simulation;
+
+ -- Divisions: div_*
+ function div_ceil(a : NATURAL; b : POSITIVE) return NATURAL is -- calculates: ceil(a / b)
+ begin
+ return (a + (b - 1)) / b;
+ end function;
+
+ -- Power functions: *_pow2
+ -- ==========================================================================
+ -- is input a power of 2?
+ function is_pow2(int : NATURAL) return BOOLEAN is
+ begin
+ return ceil_pow2(int) = int;
+ end function;
+
+ -- round to next power of 2
+ function ceil_pow2(int : NATURAL) return POSITIVE is
+ begin
+ return 2 ** log2ceil(int);
+ end function;
+
+ -- round to previous power of 2
+ function floor_pow2(int : NATURAL) return NATURAL is
+ variable temp : UNSIGNED(30 downto 0);
+ begin
+ temp := to_unsigned(int, 31);
+ for i in temp'range loop
+ if (temp(i) = '1') then
+ return 2 ** i;
+ end if;
+ end loop;
+ return 0;
+ end function;
+
+ -- Logarithms: log*ceil*
+ -- ==========================================================================
+ function log2ceil(arg : positive) return natural is
+ variable tmp : positive;
+ variable log : natural;
+ begin
+ if arg = 1 then return 0; end if;
+ tmp := 1;
+ log := 0;
+ while arg > tmp loop
+ tmp := tmp * 2;
+ log := log + 1;
+ end loop;
+ return log;
+ end function;
+
+ function log2ceilnz(arg : positive) return positive is
+ begin
+ return imax(1, log2ceil(arg));
+ end function;
+
+ function log10ceil(arg : positive) return natural is
+ variable tmp : positive;
+ variable log : natural;
+ begin
+ if arg = 1 then return 0; end if;
+ tmp := 1;
+ log := 0;
+ while arg > tmp loop
+ tmp := tmp * 10;
+ log := log + 1;
+ end loop;
+ return log;
+ end function;
+
+ function log10ceilnz(arg : positive) return positive is
+ begin
+ return imax(1, log10ceil(arg));
+ end function;
+
+ -- if-then-else (ite)
+ -- ==========================================================================
+ function ite(cond : BOOLEAN; value1 : BOOLEAN; value2 : BOOLEAN) return BOOLEAN is
+ begin
+ if cond then
+ return value1;
+ else
+ return value2;
+ end if;
+ end function;
+
+ function ite(cond : BOOLEAN; value1 : INTEGER; value2 : INTEGER) return INTEGER is
+ begin
+ if cond then
+ return value1;
+ else
+ return value2;
+ end if;
+ end function;
+
+ function ite(cond : BOOLEAN; value1 : REAL; value2 : REAL) return REAL is
+ begin
+ if cond then
+ return value1;
+ else
+ return value2;
+ end if;
+ end function;
+
+ function ite(cond : BOOLEAN; value1 : STD_LOGIC; value2 : STD_LOGIC) return STD_LOGIC is
+ begin
+ if cond then
+ return value1;
+ else
+ return value2;
+ end if;
+ end function;
+
+ function ite(cond : BOOLEAN; value1 : STD_LOGIC_VECTOR; value2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+ begin
+ if cond then
+ return value1;
+ else
+ return value2;
+ end if;
+ end function;
+
+ function ite(cond : BOOLEAN; value1 : BIT_VECTOR; value2 : BIT_VECTOR) return BIT_VECTOR is
+ begin
+ if cond then
+ return value1;
+ else
+ return value2;
+ end if;
+ end function;
+
+ function ite(cond : BOOLEAN; value1 : UNSIGNED; value2 : UNSIGNED) return UNSIGNED is
+ begin
+ if cond then
+ return value1;
+ else
+ return value2;
+ end if;
+ end function;
+
+ function ite(cond : BOOLEAN; value1 : CHARACTER; value2 : CHARACTER) return CHARACTER is
+ begin
+ if cond then
+ return value1;
+ else
+ return value2;
+ end if;
+ end function;
+
+ function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING is
+ begin
+ if cond then
+ return value1;
+ else
+ return value2;
+ end if;
+ end function;
+
+ -- *min / *max / *sum
+ -- ==========================================================================
+ function imin(arg1 : integer; arg2 : integer) return integer is
+ begin
+ if arg1 < arg2 then return arg1; end if;
+ return arg2;
+ end function;
+
+ -- function rmin(arg1 : real; arg2 : real) return real is
+ -- begin
+ -- if arg1 < arg2 then return arg1; end if;
+ -- return arg2;
+ -- end function;
+
+ function imin(vec : T_INTVEC) return INTEGER is
+ variable Result : INTEGER;
+ begin
+ Result := INTEGER'high;
+ for i in vec'range loop
+ if (vec(I) < Result) then
+ Result := vec(I);
+ end if;
+ end loop;
+ return Result;
+ end function;
+
+ function imin(vec : T_NATVEC) return NATURAL is
+ variable Result : NATURAL;
+ begin
+ Result := NATURAL'high;
+ for i in vec'range loop
+ if (vec(I) < Result) then
+ Result := vec(I);
+ end if;
+ end loop;
+ return Result;
+ end function;
+
+ function imin(vec : T_POSVEC) return POSITIVE is
+ variable Result : POSITIVE;
+ begin
+ Result := POSITIVE'high;
+ for i in vec'range loop
+ if (vec(I) < Result) then
+ Result := vec(I);
+ end if;
+ end loop;
+ return Result;
+ end function;
+
+ function rmin(vec : T_REALVEC) return REAL is
+ variable Result : REAL;
+ begin
+ Result := REAL'high;
+ for i in vec'range loop
+ if vec(i) < Result then
+ Result := vec(i);
+ end if;
+ end loop;
+ return Result;
+ end function;
+
+ function imax(arg1 : integer; arg2 : integer) return integer is
+ begin
+ if arg1 > arg2 then return arg1; end if;
+ return arg2;
+ end function;
+
+ -- function rmax(arg1 : real; arg2 : real) return real is
+ -- begin
+ -- if arg1 > arg2 then return arg1; end if;
+ -- return arg2;
+ -- end function;
+
+ function imax(vec : T_INTVEC) return INTEGER is
+ variable Result : INTEGER;
+ begin
+ Result := INTEGER'low;
+ for i in vec'range loop
+ if (vec(I) > Result) then
+ Result := vec(I);
+ end if;
+ end loop;
+ return Result;
+ end function;
+
+ function imax(vec : T_NATVEC) return NATURAL is
+ variable Result : NATURAL;
+ begin
+ Result := NATURAL'low;
+ for i in vec'range loop
+ if (vec(I) > Result) then
+ Result := vec(I);
+ end if;
+ end loop;
+ return Result;
+ end function;
+
+ function imax(vec : T_POSVEC) return POSITIVE is
+ variable Result : POSITIVE;
+ begin
+ Result := POSITIVE'low;
+ for i in vec'range loop
+ if (vec(I) > Result) then
+ Result := vec(I);
+ end if;
+ end loop;
+ return Result;
+ end function;
+
+ function rmax(vec : T_REALVEC) return REAL is
+ variable Result : REAL;
+ begin
+ Result := REAL'low;
+ for i in vec'range loop
+ if vec(i) > Result then
+ Result := vec(i);
+ end if;
+ end loop;
+ return Result;
+ end function;
+
+ function isum(vec : T_INTVEC) return INTEGER is
+ variable Result : INTEGER;
+ begin
+ Result := 0;
+ for i in vec'range loop
+ Result := Result + vec(i);
+ end loop;
+ return Result;
+ end function;
+
+ function isum(vec : T_NATVEC) return NATURAL is
+ variable Result : NATURAL;
+ begin
+ Result := 0;
+ for i in vec'range loop
+ Result := Result + vec(I);
+ end loop;
+ return Result;
+ end function;
+
+ function isum(vec : T_POSVEC) return natural is
+ variable Result : natural;
+ begin
+ Result := 0;
+ for i in vec'range loop
+ Result := Result + vec(I);
+ end loop;
+ return Result;
+ end function;
+
+ function rsum(vec : T_REALVEC) return REAL is
+ variable Result : REAL;
+ begin
+ Result := 0.0;
+ for i in vec'range loop
+ Result := Result + vec(i);
+ end loop;
+ return Result;
+ end function;
+
+ -- Vector aggregate functions: slv_*
+ -- ==========================================================================
+ function slv_or(vec : STD_LOGIC_VECTOR) return STD_LOGIC is
+ variable Result : STD_LOGIC;
+ begin
+ Result := '0';
+ for i in vec'range loop
+ Result := Result or vec(i);
+ end loop;
+ return Result;
+ end function;
+
+ function slv_nor(vec : STD_LOGIC_VECTOR) return STD_LOGIC is
+ begin
+ return not slv_or(vec);
+ end function;
+
+ function slv_and(vec : STD_LOGIC_VECTOR) return STD_LOGIC is
+ variable Result : STD_LOGIC;
+ begin
+ Result := '1';
+ for i in vec'range loop
+ Result := Result and vec(i);
+ end loop;
+ return Result;
+ end function;
+
+ function slv_nand(vec : STD_LOGIC_VECTOR) return STD_LOGIC is
+ begin
+ return not slv_and(vec);
+ end function;
+
+ function slv_xor(vec : std_logic_vector) return std_logic is
+ variable res : std_logic;
+ begin
+ res := '0';
+ for i in vec'range loop
+ res := res xor vec(i);
+ end loop;
+ return res;
+ end slv_xor;
+
+ -- Convert to integer: to_int
+ function to_int(bool : BOOLEAN; zero : INTEGER := 0; one : INTEGER := 1) return INTEGER is
+ begin
+ return ite(bool, one, zero);
+ end function;
+
+ function to_int(sl : STD_LOGIC; zero : INTEGER := 0; one : INTEGER := 1) return INTEGER is
+ begin
+ if (sl = '1') then
+ return one;
+ end if;
+ return zero;
+ end function;
+
+ -- Convert to bit: to_sl
+ -- ==========================================================================
+ function to_sl(Value : BOOLEAN) return STD_LOGIC is
+ begin
+ return ite(Value, '1', '0');
+ end function;
+
+ function to_sl(Value : CHARACTER) return STD_LOGIC is
+ begin
+ case Value is
+ when 'U' => return 'U';
+ when '0' => return '0';
+ when '1' => return '1';
+ when 'Z' => return 'Z';
+ when 'W' => return 'W';
+ when 'L' => return 'L';
+ when 'H' => return 'H';
+ when '-' => return '-';
+ when OTHERS => return 'X';
+ end case;
+ end function;
+
+ -- Convert to vector: to_slv
+ -- ==========================================================================
+ -- short for std_logic_vector(to_unsigned(Value, Size))
+ -- the return value is guaranteed to have the range (Size-1 downto 0)
+ function to_slv(Value : NATURAL; Size : POSITIVE) return STD_LOGIC_VECTOR is
+ constant res : std_logic_vector(Size-1 downto 0) := std_logic_vector(to_unsigned(Value, Size));
+ begin
+ return res;
+ end function;
+
+ function to_index(slv : UNSIGNED; max : NATURAL := 0) return INTEGER is
+ variable res : integer;
+ begin
+ if (slv'length = 0) then return 0; end if;
+
+ res := to_integer(slv);
+ if SIMULATION and max > 0 then
+ res := imin(res, max);
+ end if;
+ return res;
+ end function;
+
+ function to_index(slv : STD_LOGIC_VECTOR; max : NATURAL := 0) return INTEGER is
+ begin
+ return to_index(unsigned(slv), max);
+ end function;
+
+ -- is_*
+ -- ==========================================================================
+ function is_sl(c : CHARACTER) return BOOLEAN is
+ begin
+ case c is
+ when 'U'|'X'|'0'|'1'|'Z'|'W'|'L'|'H'|'-' => return true;
+ when OTHERS => return false;
+ end case;
+ end function;
+
+
+ -- Reverse vector elements
+ function reverse(vec : std_logic_vector) return std_logic_vector is
+ variable res : std_logic_vector(vec'range);
+ begin
+ for i in vec'low to vec'high loop
+ res(vec'low + (vec'high-i)) := vec(i);
+ end loop;
+ return res;
+ end function;
+
+ function reverse(vec : bit_vector) return bit_vector is
+ variable res : bit_vector(vec'range);
+ begin
+ res := to_bitvector(reverse(to_stdlogicvector(vec)));
+ return res;
+ end reverse;
+
+ function reverse(vec : unsigned) return unsigned is
+ begin
+ return unsigned(reverse(std_logic_vector(vec)));
+ end function;
+
+
+ -- Swap sub vectors in vector
+ -- ==========================================================================
+ function swap(slv : STD_LOGIC_VECTOR; Size : POSITIVE) return STD_LOGIC_VECTOR IS
+ CONSTANT SegmentCount : NATURAL := slv'length / Size;
+ variable FromH : NATURAL;
+ variable FromL : NATURAL;
+ variable ToH : NATURAL;
+ variable ToL : NATURAL;
+ variable Result : STD_LOGIC_VECTOR(slv'length - 1 DOWNTO 0);
+ begin
+ for i in 0 TO SegmentCount - 1 loop
+ FromH := ((I + 1) * Size) - 1;
+ FromL := I * Size;
+ ToH := ((SegmentCount - I) * Size) - 1;
+ ToL := (SegmentCount - I - 1) * Size;
+ Result(ToH DOWNTO ToL) := slv(FromH DOWNTO FromL);
+ end loop;
+ return Result;
+ end function;
+
+ -- generate bit masks
+ -- ==========================================================================
+ function genmask_high(Bits : NATURAL; MaskLength : POSITIVE) return STD_LOGIC_VECTOR IS
+ begin
+ if (Bits = 0) then
+ return (MaskLength - 1 DOWNTO 0 => '0');
+ else
+ return (MaskLength - 1 DOWNTO MaskLength - Bits + 1 => '1') & (MaskLength - Bits DOWNTO 0 => '0');
+ end if;
+ end function;
+
+ function genmask_low(Bits : NATURAL; MaskLength : POSITIVE) return STD_LOGIC_VECTOR is
+ begin
+ if (Bits = 0) then
+ return (MaskLength - 1 DOWNTO 0 => '0');
+ else
+ return (MaskLength - 1 DOWNTO Bits => '0') & (Bits - 1 DOWNTO 0 => '1');
+ end if;
+ end function;
+
+ -- binary encoding conversion functions
+ -- ==========================================================================
+ -- One-Hot-Code to Binary-Code
+ function onehot2bin(onehot : std_logic_vector) return unsigned is
+ variable res : unsigned(log2ceilnz(onehot'high+1)-1 downto 0);
+ variable chk : natural;
+ begin
+ res := (others => '0');
+ chk := 0;
+ for i in onehot'range loop
+ if onehot(i) = '1' then
+ res := res or to_unsigned(i, res'length);
+ chk := chk + 1;
+ end if;
+ end loop;
+ if SIMULATION and chk /= 1 then
+ report "Broken 1-Hot-Code with "&integer'image(chk)&" bits set."
+ severity error;
+ end if;
+ return res;
+ end onehot2bin;
+
+ -- Gray-Code to Binary-Code
+ function gray2bin(gray_val : std_logic_vector) return std_logic_vector is
+ variable res : std_logic_vector(gray_val'range);
+ begin -- gray2bin
+ res(res'left) := gray_val(gray_val'left);
+ for i in res'left-1 downto res'right loop
+ res(i) := res(i+1) xor gray_val(i);
+ end loop;
+ return res;
+ end gray2bin;
+
+ -- Binary-Code to One-Hot-Code
+ function bin2onehot(value : std_logic_vector) return std_logic_vector is
+ variable result : std_logic_vector(2**value'length - 1 downto 0);
+ begin
+ result := (others => '0');
+ result(to_index(value, 0)) := '1';
+ return result;
+ end function;
+
+ -- Binary-Code to Gray-Code
+ function bin2gray(value : std_logic_vector) return std_logic_vector is
+ variable result : std_logic_vector(value'range);
+ begin
+ result(result'left) := value(value'left);
+ for i in (result'left - 1) downto result'right loop
+ result(i) := value(i) xor value(i + 1);
+ end loop;
+ return result;
+ end function;
+
+ -- bit searching / bit indices
+ -- ==========================================================================
+ -- Least-Significant Set Bit (lssb): computes a vector of the same length with at most one bit set at the rightmost '1' found in arg.
+ function lssb(arg : std_logic_vector) return std_logic_vector is
+ variable res : std_logic_vector(arg'range);
+ begin
+ res := arg and std_logic_vector(unsigned(not arg)+1);
+ return res;
+ end function;
+
+ function lssb(arg : bit_vector) return bit_vector is
+ variable res : bit_vector(arg'range);
+ begin
+ res := to_bitvector(lssb(to_stdlogicvector(arg)));
+ return res;
+ end lssb;
+
+ -- Most-Significant Set Bit (mssb): computes a vector of the same length with at most one bit set at the leftmost '1' found in arg.
+ function mssb(arg : std_logic_vector) return std_logic_vector is
+ begin
+ return reverse(lssb(reverse(arg)));
+ end function;
+
+ function mssb(arg : bit_vector) return bit_vector is
+ begin
+ return reverse(lssb(reverse(arg)));
+ end mssb;
+
+ -- Index of lssb
+ function lssb_idx(arg : std_logic_vector) return integer is
+ begin
+ return to_integer(onehot2bin(lssb(arg)));
+ end function;
+
+ function lssb_idx(arg : bit_vector) return integer is
+ variable slv : std_logic_vector(arg'range);
+ begin
+ slv := to_stdlogicvector(arg);
+ return lssb_idx(slv);
+ end lssb_idx;
+
+ -- Index of mssb
+ function mssb_idx(arg : std_logic_vector) return integer is
+ begin
+ return to_integer(onehot2bin(mssb(arg)));
+ end function;
+
+ function mssb_idx(arg : bit_vector) return integer is
+ variable slv : std_logic_vector(arg'range);
+ begin
+ slv := to_stdlogicvector(arg);
+ return mssb_idx(slv);
+ end mssb_idx;
+
+ -- scale a value into a given range
+ function scale(Value : INTEGER; Minimum : INTEGER; Maximum : INTEGER; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
+ begin
+ return scale(real(Value), Minimum, Maximum, RoundingStyle);
+ end function;
+
+ function scale(Value : REAL; Minimum : INTEGER; Maximum : INTEGER; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
+ variable Result : REAL;
+ begin
+ if (Maximum < Minimum) then
+ return INTEGER'low;
+ else
+ Result := real(Value) * ((real(Maximum) + 0.5) - (real(Minimum) - 0.5)) + (real(Minimum) - 0.5);
+ case RoundingStyle is
+ when ROUND_TO_NEAREST => return integer(round(Result));
+ when ROUND_TO_ZERO => report "scale: unsupported RoundingStyle." severity FAILURE;
+ when ROUND_TO_INF => report "scale: unsupported RoundingStyle." severity FAILURE;
+ when ROUND_UP => return integer(ceil(Result));
+ when ROUND_DOWN => return integer(floor(Result));
+ when others => report "scale: unsupported RoundingStyle." severity FAILURE;
+ end case;
+ end if;
+ end function;
+
+ function scale(Value : REAL; Minimum : REAL; Maximum : REAL) return REAL is
+ begin
+ if (Maximum < Minimum) then
+ return REAL'low;
+ else
+ return Value * (Maximum - Minimum) + Minimum;
+ end if;
+ end function;
+
+ function resize(vec : bit_vector; length : natural; fill : bit := '0') return bit_vector is
+ constant high2b : natural := vec'low+length-1;
+ constant highcp : natural := imin(vec'high, high2b);
+ variable res_up : bit_vector(vec'low to high2b);
+ variable res_dn : bit_vector(high2b downto vec'low);
+ begin
+ if vec'ascending then
+ res_up := (others => fill);
+ res_up(vec'low to highcp) := vec(vec'low to highcp);
+ return res_up;
+ else
+ res_dn := (others => fill);
+ res_dn(highcp downto vec'low) := vec(highcp downto vec'low);
+ return res_dn;
+ end if;
+ end resize;
+
+ function resize(vec : std_logic_vector; length : natural; fill : std_logic := '0') return std_logic_vector is
+ constant high2b : natural := vec'low+length-1;
+ constant highcp : natural := imin(vec'high, high2b);
+ variable res_up : std_logic_vector(vec'low to high2b);
+ variable res_dn : std_logic_vector(high2b downto vec'low);
+ begin
+ if vec'ascending then
+ res_up := (others => fill);
+ res_up(vec'low to highcp) := vec(vec'low to highcp);
+ return res_up;
+ else
+ res_dn := (others => fill);
+ res_dn(highcp downto vec'low) := vec(highcp downto vec'low);
+ return res_dn;
+ end if;
+ end resize;
+
+ -- Move vector boundaries
+ -- ==========================================================================
+ function move(vec : std_logic_vector; ofs : integer) return std_logic_vector is
+ variable res_up : std_logic_vector(vec'low +ofs to vec'high+ofs);
+ variable res_dn : std_logic_vector(vec'high+ofs downto vec'low +ofs);
+ begin
+ if vec'ascending then
+ res_up := vec;
+ return res_up;
+ else
+ res_dn := vec;
+ return res_dn;
+ end if;
+ end move;
+
+ function movez(vec : std_logic_vector) return std_logic_vector is
+ begin
+ return move(vec, -vec'low);
+ end movez;
+
+ function ascend(vec : std_logic_vector) return std_logic_vector is
+ variable res : std_logic_vector(vec'low to vec'high);
+ begin
+ res := vec;
+ return res;
+ end ascend;
+
+ function descend(vec : std_logic_vector) return std_logic_vector is
+ variable res : std_logic_vector(vec'high downto vec'low);
+ begin
+ res := vec;
+ return res;
+ end descend;
+end package body;
diff --git a/testsuite/gna/bug037/vectors.vhdl b/testsuite/gna/bug037/vectors.vhdl new file mode 100644 index 000000000..bae1ecf46 --- /dev/null +++ b/testsuite/gna/bug037/vectors.vhdl @@ -0,0 +1,960 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+--
+-- ============================================================================
+-- Package: Common functions and types
+--
+-- Authors: Thomas B. Preusser
+-- Martin Zabel
+-- Patrick Lehmann
+--
+-- Description:
+-- ------------------------------------
+-- For detailed documentation see below.
+--
+-- License:
+-- ============================================================================
+-- Copyright 2007-2014 Technische Universitaet Dresden - Germany
+-- Chair for VLSI-Design, Diagnostics and Architecture
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- ============================================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library PoC;
+use PoC.utils.all;
+use PoC.strings.all;
+
+
+package vectors is
+ -- ==========================================================================
+ -- Type declarations
+ -- ==========================================================================
+ -- STD_LOGIC_VECTORs
+ subtype T_SLV_2 is STD_LOGIC_VECTOR(1 downto 0);
+ subtype T_SLV_3 is STD_LOGIC_VECTOR(2 downto 0);
+ subtype T_SLV_4 is STD_LOGIC_VECTOR(3 downto 0);
+ subtype T_SLV_8 is STD_LOGIC_VECTOR(7 downto 0);
+ subtype T_SLV_12 is STD_LOGIC_VECTOR(11 downto 0);
+ subtype T_SLV_16 is STD_LOGIC_VECTOR(15 downto 0);
+ subtype T_SLV_24 is STD_LOGIC_VECTOR(23 downto 0);
+ subtype T_SLV_32 is STD_LOGIC_VECTOR(31 downto 0);
+ subtype T_SLV_48 is STD_LOGIC_VECTOR(47 downto 0);
+ subtype T_SLV_64 is STD_LOGIC_VECTOR(63 downto 0);
+ subtype T_SLV_96 is STD_LOGIC_VECTOR(95 downto 0);
+ subtype T_SLV_128 is STD_LOGIC_VECTOR(127 downto 0);
+ subtype T_SLV_256 is STD_LOGIC_VECTOR(255 downto 0);
+ subtype T_SLV_512 is STD_LOGIC_VECTOR(511 downto 0);
+
+ -- STD_LOGIC_VECTOR_VECTORs
+ -- type T_SLVV is array(NATURAL range <>) of STD_LOGIC_VECTOR; -- VHDL 2008 syntax - not yet supported by Xilinx
+ type T_SLVV_2 is array(NATURAL range <>) of T_SLV_2;
+ type T_SLVV_3 is array(NATURAL range <>) of T_SLV_3;
+ type T_SLVV_4 is array(NATURAL range <>) of T_SLV_4;
+ type T_SLVV_8 is array(NATURAL range <>) of T_SLV_8;
+ type T_SLVV_12 is array(NATURAL range <>) of T_SLV_12;
+ type T_SLVV_16 is array(NATURAL range <>) of T_SLV_16;
+ type T_SLVV_24 is array(NATURAL range <>) of T_SLV_24;
+ type T_SLVV_32 is array(NATURAL range <>) of T_SLV_32;
+ type T_SLVV_48 is array(NATURAL range <>) of T_SLV_48;
+ type T_SLVV_64 is array(NATURAL range <>) of T_SLV_64;
+ type T_SLVV_128 is array(NATURAL range <>) of T_SLV_128;
+ type T_SLVV_256 is array(NATURAL range <>) of T_SLV_256;
+ type T_SLVV_512 is array(NATURAL range <>) of T_SLV_512;
+
+ -- STD_LOGIC_MATRIXs
+ type T_SLM is array(NATURAL range <>, NATURAL range <>) of STD_LOGIC;
+ -- ATTENTION:
+ -- 1. you MUST initialize your matrix signal with 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave)
+ -- Example: signal myMatrix : T_SLM(3 downto 0, 7 downto 0) := (others => (others => 'Z'));
+ -- 2. Xilinx iSIM work-around: DON'T use myMatrix'range(n) for n >= 2
+ -- because: myMatrix'range(2) returns always myMatrix'range(1); tested with ISE/iSIM 14.2
+ -- USAGE NOTES:
+ -- dimmension 1 => rows - e.g. Words
+ -- dimmension 2 => columns - e.g. Bits/Bytes in a word
+
+
+ -- ==========================================================================
+ -- Function declarations
+ -- ==========================================================================
+ -- slicing boundary calulations
+ function low (lenvec : T_POSVEC; index : NATURAL) return NATURAL;
+ function high(lenvec : T_POSVEC; index : NATURAL) return NATURAL;
+
+ -- Assign procedures: assign_*
+ procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL); -- assign vector to complete row
+ procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL; Position : NATURAL); -- assign short vector to row starting at position
+ procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL; High : NATURAL; Low : NATURAL); -- assign short vector to row in range high:low
+ procedure assign_col(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant ColIndex : NATURAL); -- assign vector to complete column
+ -- ATTENTION: see T_SLM definition for further details and work-arounds
+
+ -- Matrix to matrix conversion: slm_slice*
+ function slm_slice(slm : T_SLM; RowIndex : NATURAL; ColIndex : NATURAL; Height : NATURAL; Width : NATURAL) return T_SLM; -- get submatrix in boundingbox RowIndex,ColIndex,Height,Width
+ function slm_slice_rows(slm : T_SLM; High : NATURAL; Low : NATURAL) return T_SLM; -- get submatrix / all rows in RowIndex range high:low
+ function slm_slice_cols(slm : T_SLM; High : NATURAL; Low : NATURAL) return T_SLM; -- get submatrix / all columns in ColIndex range high:low
+
+ -- Matrix concatenation: slm_merge_*
+ function slm_merge_rows(slm1 : T_SLM; slm2 : T_SLM) return T_SLM;
+ function slm_merge_cols(slm1 : T_SLM; slm2 : T_SLM) return T_SLM;
+
+ -- Matrix to vector conversion: get_*
+ function get_col(slm : T_SLM; ColIndex : NATURAL) return STD_LOGIC_VECTOR; -- get a matrix column
+ function get_row(slm : T_SLM; RowIndex : NATURAL) return STD_LOGIC_VECTOR; -- get a matrix row
+ function get_row(slm : T_SLM; RowIndex : NATURAL; Length : POSITIVE) return STD_LOGIC_VECTOR; -- get a matrix row of defined length [length - 1 downto 0]
+ function get_row(slm : T_SLM; RowIndex : NATURAL; High : NATURAL; Low : NATURAL) return STD_LOGIC_VECTOR; -- get a sub vector of a matrix row at high:low
+
+ -- Convert to vector: to_slv
+ function to_slv(slvv : T_SLVV_2) return STD_LOGIC_VECTOR; -- convert vector-vector to flatten vector
+ function to_slv(slvv : T_SLVV_4) return STD_LOGIC_VECTOR; -- ...
+ function to_slv(slvv : T_SLVV_8) return STD_LOGIC_VECTOR; -- ...
+ function to_slv(slvv : T_SLVV_12) return STD_LOGIC_VECTOR; -- ...
+ function to_slv(slvv : T_SLVV_16) return STD_LOGIC_VECTOR; -- ...
+ function to_slv(slvv : T_SLVV_24) return STD_LOGIC_VECTOR; -- ...
+ function to_slv(slvv : T_SLVV_32) return STD_LOGIC_VECTOR; -- ...
+ function to_slv(slvv : T_SLVV_64) return STD_LOGIC_VECTOR; -- ...
+ function to_slv(slvv : T_SLVV_128) return STD_LOGIC_VECTOR; -- ...
+ function to_slv(slm : T_SLM) return STD_LOGIC_VECTOR; -- convert matrix to flatten vector
+
+ -- Convert flat vector to avector-vector: to_slvv_*
+ function to_slvv_4(slv : STD_LOGIC_VECTOR) return T_SLVV_4; --
+ function to_slvv_8(slv : STD_LOGIC_VECTOR) return T_SLVV_8; --
+ function to_slvv_12(slv : STD_LOGIC_VECTOR) return T_SLVV_12; --
+ function to_slvv_16(slv : STD_LOGIC_VECTOR) return T_SLVV_16; --
+ function to_slvv_32(slv : STD_LOGIC_VECTOR) return T_SLVV_32; --
+ function to_slvv_64(slv : STD_LOGIC_VECTOR) return T_SLVV_64; --
+ function to_slvv_128(slv : STD_LOGIC_VECTOR) return T_SLVV_128; --
+ function to_slvv_256(slv : STD_LOGIC_VECTOR) return T_SLVV_256; --
+ function to_slvv_512(slv : STD_LOGIC_VECTOR) return T_SLVV_512; --
+
+ -- Convert matrix to avector-vector: to_slvv_*
+ function to_slvv_4(slm : T_SLM) return T_SLVV_4; --
+ function to_slvv_8(slm : T_SLM) return T_SLVV_8; --
+ function to_slvv_12(slm : T_SLM) return T_SLVV_12; --
+ function to_slvv_16(slm : T_SLM) return T_SLVV_16; --
+ function to_slvv_32(slm : T_SLM) return T_SLVV_32; --
+ function to_slvv_64(slm : T_SLM) return T_SLVV_64; --
+ function to_slvv_128(slm : T_SLM) return T_SLVV_128; --
+ function to_slvv_256(slm : T_SLM) return T_SLVV_256; --
+ function to_slvv_512(slm : T_SLM) return T_SLVV_512; --
+
+ -- Convert vector-vector to matrix: to_slm
+ function to_slm(slv : STD_LOGIC_VECTOR; ROWS : POSITIVE; COLS : POSITIVE) return T_SLM; -- create matrix from vector
+ function to_slm(slvv : T_SLVV_4) return T_SLM; -- create matrix from vector-vector
+ function to_slm(slvv : T_SLVV_8) return T_SLM; -- create matrix from vector-vector
+ function to_slm(slvv : T_SLVV_12) return T_SLM; -- create matrix from vector-vector
+ function to_slm(slvv : T_SLVV_16) return T_SLM; -- create matrix from vector-vector
+ function to_slm(slvv : T_SLVV_32) return T_SLM; -- create matrix from vector-vector
+ function to_slm(slvv : T_SLVV_48) return T_SLM; -- create matrix from vector-vector
+ function to_slm(slvv : T_SLVV_64) return T_SLM; -- create matrix from vector-vector
+ function to_slm(slvv : T_SLVV_128) return T_SLM; -- create matrix from vector-vector
+ function to_slm(slvv : T_SLVV_256) return T_SLM; -- create matrix from vector-vector
+ function to_slm(slvv : T_SLVV_512) return T_SLM; -- create matrix from vector-vector
+
+ -- Change vector direction
+ function dir(slvv : T_SLVV_8) return T_SLVV_8;
+
+ -- Reverse vector elements
+ function rev(slvv : T_SLVV_4) return T_SLVV_4;
+ function rev(slvv : T_SLVV_8) return T_SLVV_8;
+ function rev(slvv : T_SLVV_12) return T_SLVV_12;
+ function rev(slvv : T_SLVV_16) return T_SLVV_16;
+ function rev(slvv : T_SLVV_32) return T_SLVV_32;
+ function rev(slvv : T_SLVV_64) return T_SLVV_64;
+ function rev(slvv : T_SLVV_128) return T_SLVV_128;
+ function rev(slvv : T_SLVV_256) return T_SLVV_256;
+ function rev(slvv : T_SLVV_512) return T_SLVV_512;
+
+ -- TODO:
+ function resize(slm : T_SLM; size : POSITIVE) return T_SLM;
+
+ -- to_string
+ function to_string(slvv : T_SLVV_8; sep : CHARACTER := ':') return STRING;
+ function to_string(slm : T_SLM; groups : POSITIVE := 4; format : CHARACTER := 'b') return STRING;
+end package vectors;
+
+
+package body vectors is
+ -- slicing boundary calulations
+ -- ==========================================================================
+ function low(lenvec : T_POSVEC; index : NATURAL) return NATURAL is
+ variable pos : NATURAL := 0;
+ begin
+ for i in lenvec'low to index - 1 loop
+ pos := pos + lenvec(i);
+ end loop;
+ return pos;
+ end function;
+
+ function high(lenvec : T_POSVEC; index : NATURAL) return NATURAL is
+ variable pos : NATURAL := 0;
+ begin
+ for i in lenvec'low to index loop
+ pos := pos + lenvec(i);
+ end loop;
+ return pos - 1;
+ end function;
+
+ -- Assign procedures: assign_*
+ -- ==========================================================================
+ procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL) is
+ variable temp : STD_LOGIC_VECTOR(slm'high(2) downto slm'low(2)); -- Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); tested with ISE/iSIM 14.2
+ begin
+ temp := slv;
+ for i in temp'range loop
+ slm(RowIndex, i) <= temp(i);
+ end loop;
+ end procedure;
+
+ procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL; Position : NATURAL) is
+ variable temp : STD_LOGIC_VECTOR(Position + slv'length - 1 downto Position);
+ begin
+ temp := slv;
+ for i in temp'range loop
+ slm(RowIndex, i) <= temp(i);
+ end loop;
+ end procedure;
+
+ procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL; High : NATURAL; Low : NATURAL) is
+ variable temp : STD_LOGIC_VECTOR(High downto Low);
+ begin
+ temp := slv;
+ for i in temp'range loop
+ slm(RowIndex, i) <= temp(i);
+ end loop;
+ end procedure;
+
+ procedure assign_col(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant ColIndex : NATURAL) is
+ variable temp : STD_LOGIC_VECTOR(slm'range(1));
+ begin
+ temp := slv;
+ for i in temp'range loop
+ slm(i, ColIndex) <= temp(i);
+ end loop;
+ end procedure;
+
+ -- Matrix to matrix conversion: slm_slice*
+ -- ==========================================================================
+ function slm_slice(slm : T_SLM; RowIndex : NATURAL; ColIndex : NATURAL; Height : NATURAL; Width : NATURAL) return T_SLM is
+ variable Result : T_SLM(Height - 1 downto 0, Width - 1 downto 0) := (others => (others => '0'));
+ begin
+ for i in 0 to Height - 1 loop
+ for j in 0 to Width - 1 loop
+ Result(i, j) := slm(RowIndex + i, ColIndex + j);
+ end loop;
+ end loop;
+ return Result;
+ end function;
+
+ function slm_slice_rows(slm : T_SLM; High : NATURAL; Low : NATURAL) return T_SLM is
+ variable Result : T_SLM(High - Low downto 0, slm'length(2) - 1 downto 0) := (others => (others => '0'));
+ begin
+ for i in 0 to High - Low loop
+ for j in 0 to slm'length(2) - 1 loop
+ Result(i, j) := slm(Low + i, slm'low(2) + j);
+ end loop;
+ end loop;
+ return Result;
+ end function;
+
+ function slm_slice_cols(slm : T_SLM; High : NATURAL; Low : NATURAL) return T_SLM is
+ variable Result : T_SLM(slm'length(1) - 1 downto 0, High - Low downto 0) := (others => (others => '0'));
+ begin
+ for i in 0 to slm'length(1) - 1 loop
+ for j in 0 to High - Low loop
+ Result(i, j) := slm(slm'low(1) + i, Low + j);
+ end loop;
+ end loop;
+ return Result;
+ end function;
+
+ -- Matrix concatenation: slm_merge_*
+ function slm_merge_rows(slm1 : T_SLM; slm2 : T_SLM) return T_SLM is
+ constant ROWS : POSITIVE := slm1'length(1) + slm2'length(1);
+ constant COLUMNS : POSITIVE := slm1'length(2);
+ variable slm : T_SLM(ROWS - 1 downto 0, COLUMNS - 1 downto 0);
+ begin
+ for i in slm1'range(1) loop
+ for j in slm1'low(2) to slm1'high(2) loop
+ slm(i, j) := slm1(i, j);
+ end loop;
+ end loop;
+ for i in slm2'range(1) loop
+ for j in slm2'low(2) to slm2'high(2) loop
+ slm(slm1'length(1) + i, j) := slm2(i, j);
+ end loop;
+ end loop;
+ return slm;
+ end function;
+
+ function slm_merge_cols(slm1 : T_SLM; slm2 : T_SLM) return T_SLM is
+ constant ROWS : POSITIVE := slm1'length(1);
+ constant COLUMNS : POSITIVE := slm1'length(2) + slm2'length(2);
+ variable slm : T_SLM(ROWS - 1 downto 0, COLUMNS - 1 downto 0);
+ begin
+ for i in slm1'range(1) loop
+ for j in slm1'low(2) to slm1'high(2) loop
+ slm(i, j) := slm1(i, j);
+ end loop;
+ for j in slm2'low(2) to slm2'high(2) loop
+ slm(i, slm1'length(2) + j) := slm2(i, j);
+ end loop;
+ end loop;
+ return slm;
+ end function;
+
+
+ -- Matrix to vector conversion: get_*
+ -- ==========================================================================
+ -- get a matrix column
+ function get_col(slm : T_SLM; ColIndex : NATURAL) return STD_LOGIC_VECTOR is
+ variable slv : STD_LOGIC_VECTOR(slm'range(1));
+ begin
+ for i in slm'range(1) loop
+ slv(i) := slm(i, ColIndex);
+ end loop;
+ return slv;
+ end function;
+
+ -- get a matrix row
+ function get_row(slm : T_SLM; RowIndex : NATURAL) return STD_LOGIC_VECTOR is
+ variable slv : STD_LOGIC_VECTOR(slm'high(2) downto slm'low(2)); -- Xilinx iSIM work-around, because 'range(2) = 'range(1); tested with ISE/iSIM 14.2
+ begin
+ for i in slv'range loop
+ slv(i) := slm(RowIndex, i);
+ end loop;
+ return slv;
+ end function;
+
+ -- get a matrix row of defined length [length - 1 downto 0]
+ function get_row(slm : T_SLM; RowIndex : NATURAL; Length : POSITIVE) return STD_LOGIC_VECTOR is
+ begin
+ return get_row(slm, RowIndex, (Length - 1), 0);
+ end function;
+
+ -- get a sub vector of a matrix row at high:low
+ function get_row(slm : T_SLM; RowIndex : NATURAL; High : NATURAL; Low : NATURAL) return STD_LOGIC_VECTOR is
+ variable slv : STD_LOGIC_VECTOR(High downto Low); -- Xilinx iSIM work-around, because 'range(2) = 'range(1); tested with ISE/iSIM 14.2
+ begin
+ for i in slv'range loop
+ slv(i) := slm(RowIndex, i);
+ end loop;
+ return slv;
+ end function;
+
+ -- Convert to vector: to_slv
+ -- ==========================================================================
+ -- convert vector-vector to flatten vector
+ function to_slv(slvv : T_SLVV_2) return STD_LOGIC_VECTOR is
+ variable slv : STD_LOGIC_VECTOR((slvv'length * 2) - 1 downto 0);
+ begin
+ for i in slvv'range loop
+ slv((i * 2) + 1 downto (i * 2)) := slvv(i);
+ end loop;
+ return slv;
+ end function;
+
+ function to_slv(slvv : T_SLVV_4) return STD_LOGIC_VECTOR is
+ variable slv : STD_LOGIC_VECTOR((slvv'length * 4) - 1 downto 0);
+ begin
+ for i in slvv'range loop
+ slv((i * 4) + 3 downto (i * 4)) := slvv(i);
+ end loop;
+ return slv;
+ end function;
+
+ function to_slv(slvv : T_SLVV_8) return STD_LOGIC_VECTOR is
+ variable slv : STD_LOGIC_VECTOR((slvv'length * 8) - 1 downto 0);
+ begin
+ for i in slvv'range loop
+ slv((i * 8) + 7 downto (i * 8)) := slvv(i);
+ end loop;
+ return slv;
+ end function;
+
+ function to_slv(slvv : T_SLVV_12) return STD_LOGIC_VECTOR is
+ variable slv : STD_LOGIC_VECTOR((slvv'length * 12) - 1 downto 0);
+ begin
+ for i in slvv'range loop
+ slv((i * 12) + 11 downto (i * 12)) := slvv(i);
+ end loop;
+ return slv;
+ end function;
+
+ function to_slv(slvv : T_SLVV_16) return STD_LOGIC_VECTOR is
+ variable slv : STD_LOGIC_VECTOR((slvv'length * 16) - 1 downto 0);
+ begin
+ for i in slvv'range loop
+ slv((i * 16) + 15 downto (i * 16)) := slvv(i);
+ end loop;
+ return slv;
+ end function;
+
+ function to_slv(slvv : T_SLVV_24) return STD_LOGIC_VECTOR is
+ variable slv : STD_LOGIC_VECTOR((slvv'length * 24) - 1 downto 0);
+ begin
+ for i in slvv'range loop
+ slv((i * 24) + 23 downto (i * 24)) := slvv(i);
+ end loop;
+ return slv;
+ end function;
+
+ function to_slv(slvv : T_SLVV_32) return STD_LOGIC_VECTOR is
+ variable slv : STD_LOGIC_VECTOR((slvv'length * 32) - 1 downto 0);
+ begin
+ for i in slvv'range loop
+ slv((i * 32) + 31 downto (i * 32)) := slvv(i);
+ end loop;
+ return slv;
+ end function;
+
+ function to_slv(slvv : T_SLVV_64) return STD_LOGIC_VECTOR is
+ variable slv : STD_LOGIC_VECTOR((slvv'length * 64) - 1 downto 0);
+ begin
+ for i in slvv'range loop
+ slv((i * 64) + 63 downto (i * 64)) := slvv(i);
+ end loop;
+ return slv;
+ end function;
+
+ function to_slv(slvv : T_SLVV_128) return STD_LOGIC_VECTOR is
+ variable slv : STD_LOGIC_VECTOR((slvv'length * 128) - 1 downto 0);
+ begin
+ for i in slvv'range loop
+ slv((i * 128) + 127 downto (i * 128)) := slvv(i);
+ end loop;
+ return slv;
+ end function;
+
+ -- convert matrix to flatten vector
+ function to_slv(slm : T_SLM) return STD_LOGIC_VECTOR is
+ variable slv : STD_LOGIC_VECTOR((slm'length(1) * slm'length(2)) - 1 downto 0);
+ begin
+ for i in slm'range(1) loop
+ for j in slm'high(2) downto slm'low(2) loop -- Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); tested with ISE/iSIM 14.2
+ slv((i * slm'length(2)) + j) := slm(i, j);
+ end loop;
+ end loop;
+ return slv;
+ end function;
+
+
+ -- Convert flat vector to a vector-vector: to_slvv_*
+ -- ==========================================================================
+ -- create vector-vector from vector (4 bit)
+ function to_slvv_4(slv : STD_LOGIC_VECTOR) return T_SLVV_4 is
+ variable Result : T_SLVV_4((slv'length / 4) - 1 downto 0);
+ begin
+ if ((slv'length mod 4) /= 0) then report "to_slvv_4: width mismatch - slv'length is no multiple of 4 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
+
+ for i in Result'range loop
+ Result(i) := slv((i * 4) + 3 downto (i * 4));
+ end loop;
+ return Result;
+ end function;
+
+ -- create vector-vector from vector (8 bit)
+ function to_slvv_8(slv : STD_LOGIC_VECTOR) return T_SLVV_8 is
+ variable Result : T_SLVV_8((slv'length / 8) - 1 downto 0);
+ begin
+ if ((slv'length mod 8) /= 0) then report "to_slvv_8: width mismatch - slv'length is no multiple of 8 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
+
+ for i in Result'range loop
+ Result(i) := slv((i * 8) + 7 downto (i * 8));
+ end loop;
+ return Result;
+ end function;
+
+ -- create vector-vector from vector (12 bit)
+ function to_slvv_12(slv : STD_LOGIC_VECTOR) return T_SLVV_12 is
+ variable Result : T_SLVV_12((slv'length / 12) - 1 downto 0);
+ begin
+ if ((slv'length mod 12) /= 0) then report "to_slvv_12: width mismatch - slv'length is no multiple of 12 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
+
+ for i in Result'range loop
+ Result(i) := slv((i * 12) + 11 downto (i * 12));
+ end loop;
+ return Result;
+ end function;
+
+ -- create vector-vector from vector (16 bit)
+ function to_slvv_16(slv : STD_LOGIC_VECTOR) return T_SLVV_16 is
+ variable Result : T_SLVV_16((slv'length / 16) - 1 downto 0);
+ begin
+ if ((slv'length mod 16) /= 0) then report "to_slvv_16: width mismatch - slv'length is no multiple of 16 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
+
+ for i in Result'range loop
+ Result(i) := slv((i * 16) + 15 downto (i * 16));
+ end loop;
+ return Result;
+ end function;
+
+ -- create vector-vector from vector (32 bit)
+ function to_slvv_32(slv : STD_LOGIC_VECTOR) return T_SLVV_32 is
+ variable Result : T_SLVV_32((slv'length / 32) - 1 downto 0);
+ begin
+ if ((slv'length mod 32) /= 0) then report "to_slvv_32: width mismatch - slv'length is no multiple of 32 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
+
+ for i in Result'range loop
+ Result(i) := slv((i * 32) + 31 downto (i * 32));
+ end loop;
+ return Result;
+ end function;
+
+ -- create vector-vector from vector (64 bit)
+ function to_slvv_64(slv : STD_LOGIC_VECTOR) return T_SLVV_64 is
+ variable Result : T_SLVV_64((slv'length / 64) - 1 downto 0);
+ begin
+ if ((slv'length mod 64) /= 0) then report "to_slvv_64: width mismatch - slv'length is no multiple of 64 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
+
+ for i in Result'range loop
+ Result(i) := slv((i * 64) + 63 downto (i * 64));
+ end loop;
+ return Result;
+ end function;
+
+ -- create vector-vector from vector (128 bit)
+ function to_slvv_128(slv : STD_LOGIC_VECTOR) return T_SLVV_128 is
+ variable Result : T_SLVV_128((slv'length / 128) - 1 downto 0);
+ begin
+ if ((slv'length mod 128) /= 0) then report "to_slvv_128: width mismatch - slv'length is no multiple of 128 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
+
+ for i in Result'range loop
+ Result(i) := slv((i * 128) + 127 downto (i * 128));
+ end loop;
+ return Result;
+ end function;
+
+ -- create vector-vector from vector (256 bit)
+ function to_slvv_256(slv : STD_LOGIC_VECTOR) return T_SLVV_256 is
+ variable Result : T_SLVV_256((slv'length / 256) - 1 downto 0);
+ begin
+ if ((slv'length mod 256) /= 0) then report "to_slvv_256: width mismatch - slv'length is no multiple of 256 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
+
+ for i in Result'range loop
+ Result(i) := slv((i * 256) + 255 downto (i * 256));
+ end loop;
+ return Result;
+ end function;
+
+ -- create vector-vector from vector (512 bit)
+ function to_slvv_512(slv : STD_LOGIC_VECTOR) return T_SLVV_512 is
+ variable Result : T_SLVV_512((slv'length / 512) - 1 downto 0);
+ begin
+ if ((slv'length mod 512) /= 0) then report "to_slvv_512: width mismatch - slv'length is no multiple of 512 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
+
+ for i in Result'range loop
+ Result(i) := slv((i * 512) + 511 downto (i * 512));
+ end loop;
+ return Result;
+ end function;
+
+ -- Convert matrix to avector-vector: to_slvv_*
+ -- ==========================================================================
+ -- create vector-vector from matrix (4 bit)
+ function to_slvv_4(slm : T_SLM) return T_SLVV_4 is
+ variable Result : T_SLVV_4(slm'range(1));
+ begin
+ if (slm'length(2) /= 4) then report "to_slvv_4: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
+
+ for i in slm'range(1) loop
+ Result(i) := get_row(slm, i);
+ end loop;
+ return Result;
+ end function;
+
+ -- create vector-vector from matrix (8 bit)
+ function to_slvv_8(slm : T_SLM) return T_SLVV_8 is
+ variable Result : T_SLVV_8(slm'range(1));
+ begin
+ if (slm'length(2) /= 8) then report "to_slvv_8: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
+
+ for i in slm'range(1) loop
+ Result(i) := get_row(slm, i);
+ end loop;
+ return Result;
+ end function;
+
+ -- create vector-vector from matrix (12 bit)
+ function to_slvv_12(slm : T_SLM) return T_SLVV_12 is
+ variable Result : T_SLVV_12(slm'range(1));
+ begin
+ if (slm'length(2) /= 12) then report "to_slvv_12: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
+
+ for i in slm'range(1) loop
+ Result(i) := get_row(slm, i);
+ end loop;
+ return Result;
+ end function;
+
+ -- create vector-vector from matrix (16 bit)
+ function to_slvv_16(slm : T_SLM) return T_SLVV_16 is
+ variable Result : T_SLVV_16(slm'range(1));
+ begin
+ if (slm'length(2) /= 16) then report "to_slvv_16: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
+
+ for i in slm'range(1) loop
+ Result(i) := get_row(slm, i);
+ end loop;
+ return Result;
+ end function;
+
+ -- create vector-vector from matrix (32 bit)
+ function to_slvv_32(slm : T_SLM) return T_SLVV_32 is
+ variable Result : T_SLVV_32(slm'range(1));
+ begin
+ if (slm'length(2) /= 32) then report "to_slvv_32: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
+
+ for i in slm'range(1) loop
+ Result(i) := get_row(slm, i);
+ end loop;
+ return Result;
+ end function;
+
+ -- create vector-vector from matrix (64 bit)
+ function to_slvv_64(slm : T_SLM) return T_SLVV_64 is
+ variable Result : T_SLVV_64(slm'range(1));
+ begin
+ if (slm'length(2) /= 64) then report "to_slvv_64: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
+
+ for i in slm'range(1) loop
+ Result(i) := get_row(slm, i);
+ end loop;
+ return Result;
+ end function;
+
+ -- create vector-vector from matrix (128 bit)
+ function to_slvv_128(slm : T_SLM) return T_SLVV_128 is
+ variable Result : T_SLVV_128(slm'range(1));
+ begin
+ if (slm'length(2) /= 128) then report "to_slvv_128: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
+
+ for i in slm'range(1) loop
+ Result(i) := get_row(slm, i);
+ end loop;
+ return Result;
+ end function;
+
+ -- create vector-vector from matrix (256 bit)
+ function to_slvv_256(slm : T_SLM) return T_SLVV_256 is
+ variable Result : T_SLVV_256(slm'range);
+ begin
+ if (slm'length(2) /= 256) then report "to_slvv_256: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
+
+ for i in slm'range loop
+ Result(i) := get_row(slm, i);
+ end loop;
+ return Result;
+ end function;
+
+ -- create vector-vector from matrix (512 bit)
+ function to_slvv_512(slm : T_SLM) return T_SLVV_512 is
+ variable Result : T_SLVV_512(slm'range(1));
+ begin
+ if (slm'length(2) /= 512) then report "to_slvv_512: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
+
+ for i in slm'range(1) loop
+ Result(i) := get_row(slm, i);
+ end loop;
+ return Result;
+ end function;
+
+ -- Convert vector-vector to matrix: to_slm
+ -- ==========================================================================
+ -- create matrix from vector
+ function to_slm(slv : STD_LOGIC_VECTOR; ROWS : POSITIVE; COLS : POSITIVE) return T_SLM is
+ variable slm : T_SLM(ROWS - 1 downto 0, COLS - 1 downto 0);
+ begin
+ for i in 0 to ROWS - 1 loop
+ for j in 0 to COLS - 1 loop
+ slm(i, j) := slv((i * COLS) + j);
+ end loop;
+ end loop;
+ return slm;
+ end function;
+
+ -- create matrix from vector-vector
+ function to_slm(slvv : T_SLVV_4) return T_SLM is
+ variable slm : T_SLM(slvv'range, 3 downto 0);
+ begin
+ for i in slvv'range loop
+ for j in T_SLV_4'range loop
+ slm(i, j) := slvv(i)(j);
+ end loop;
+ end loop;
+ return slm;
+ end function;
+
+ function to_slm(slvv : T_SLVV_8) return T_SLM is
+-- variable test : STD_LOGIC_VECTOR(T_SLV_8'range);
+-- variable slm : T_SLM(slvv'range, test'range); -- BUG: iSIM 14.5 cascaded 'range accesses let iSIM break down
+-- variable slm : T_SLM(slvv'range, T_SLV_8'range); -- BUG: iSIM 14.5 allocates 9 bits in dimmension 2
+ variable slm : T_SLM(slvv'range, 7 downto 0);
+ begin
+-- report "slvv: slvv.length=" & INTEGER'image(slvv'length) & " slm.dim0.length=" & INTEGER'image(slm'length(1)) & " slm.dim1.length=" & INTEGER'image(slm'length(2)) severity NOTE;
+-- report "T_SLV_8: .length=" & INTEGER'image(T_SLV_8'length) & " .high=" & INTEGER'image(T_SLV_8'high) & " .low=" & INTEGER'image(T_SLV_8'low) severity NOTE;
+-- report "test: test.length=" & INTEGER'image(test'length) & " .high=" & INTEGER'image(test'high) & " .low=" & INTEGER'image(test'low) severity NOTE;
+ for i in slvv'range loop
+ for j in T_SLV_8'range loop
+ slm(i, j) := slvv(i)(j);
+ end loop;
+ end loop;
+ return slm;
+ end function;
+
+ function to_slm(slvv : T_SLVV_12) return T_SLM is
+ variable slm : T_SLM(slvv'range, 11 downto 0);
+ begin
+ for i in slvv'range loop
+ for j in T_SLV_12'range loop
+ slm(i, j) := slvv(i)(j);
+ end loop;
+ end loop;
+ return slm;
+ end function;
+
+ function to_slm(slvv : T_SLVV_16) return T_SLM is
+ variable slm : T_SLM(slvv'range, 15 downto 0);
+ begin
+ for i in slvv'range loop
+ for j in T_SLV_16'range loop
+ slm(i, j) := slvv(i)(j);
+ end loop;
+ end loop;
+ return slm;
+ end function;
+
+ function to_slm(slvv : T_SLVV_32) return T_SLM is
+ variable slm : T_SLM(slvv'range, 31 downto 0);
+ begin
+ for i in slvv'range loop
+ for j in T_SLV_32'range loop
+ slm(i, j) := slvv(i)(j);
+ end loop;
+ end loop;
+ return slm;
+ end function;
+
+ function to_slm(slvv : T_SLVV_48) return T_SLM is
+ variable slm : T_SLM(slvv'range, 47 downto 0);
+ begin
+ for i in slvv'range loop
+ for j in T_SLV_48'range loop
+ slm(i, j) := slvv(i)(j);
+ end loop;
+ end loop;
+ return slm;
+ end function;
+
+ function to_slm(slvv : T_SLVV_64) return T_SLM is
+ variable slm : T_SLM(slvv'range, 63 downto 0);
+ begin
+ for i in slvv'range loop
+ for j in T_SLV_64'range loop
+ slm(i, j) := slvv(i)(j);
+ end loop;
+ end loop;
+ return slm;
+ end function;
+
+ function to_slm(slvv : T_SLVV_128) return T_SLM is
+ variable slm : T_SLM(slvv'range, 127 downto 0);
+ begin
+ for i in slvv'range loop
+ for j in T_SLV_128'range loop
+ slm(i, j) := slvv(i)(j);
+ end loop;
+ end loop;
+ return slm;
+ end function;
+
+ function to_slm(slvv : T_SLVV_256) return T_SLM is
+ variable slm : T_SLM(slvv'range, 255 downto 0);
+ begin
+ for i in slvv'range loop
+ for j in T_SLV_256'range loop
+ slm(i, j) := slvv(i)(j);
+ end loop;
+ end loop;
+ return slm;
+ end function;
+
+ function to_slm(slvv : T_SLVV_512) return T_SLM is
+ variable slm : T_SLM(slvv'range, 511 downto 0);
+ begin
+ for i in slvv'range loop
+ for j in T_SLV_512'range loop
+ slm(i, j) := slvv(i)(j);
+ end loop;
+ end loop;
+ return slm;
+ end function;
+
+ -- Change vector direction
+ -- ==========================================================================
+ function dir(slvv : T_SLVV_8) return T_SLVV_8 is
+ variable Result : T_SLVV_8(slvv'reverse_range);
+ begin
+ Result := slvv;
+ return Result;
+ end function;
+
+ -- Reverse vector elements
+ function rev(slvv : T_SLVV_4) return T_SLVV_4 is
+ variable Result : T_SLVV_4(slvv'range);
+ begin
+ for i in slvv'low to slvv'high loop
+ Result(slvv'high - i) := slvv(i);
+ end loop;
+ return Result;
+ end function;
+
+ function rev(slvv : T_SLVV_8) return T_SLVV_8 is
+ variable Result : T_SLVV_8(slvv'range);
+ begin
+ for i in slvv'low to slvv'high loop
+ Result(slvv'high - i) := slvv(i);
+ end loop;
+ return Result;
+ end function;
+
+ function rev(slvv : T_SLVV_12) return T_SLVV_12 is
+ variable Result : T_SLVV_12(slvv'range);
+ begin
+ for i in slvv'low to slvv'high loop
+ Result(slvv'high - i) := slvv(i);
+ end loop;
+ return Result;
+ end function;
+
+ function rev(slvv : T_SLVV_16) return T_SLVV_16 is
+ variable Result : T_SLVV_16(slvv'range);
+ begin
+ for i in slvv'low to slvv'high loop
+ Result(slvv'high - i) := slvv(i);
+ end loop;
+ return Result;
+ end function;
+
+ function rev(slvv : T_SLVV_32) return T_SLVV_32 is
+ variable Result : T_SLVV_32(slvv'range);
+ begin
+ for i in slvv'low to slvv'high loop
+ Result(slvv'high - i) := slvv(i);
+ end loop;
+ return Result;
+ end function;
+
+ function rev(slvv : T_SLVV_64) return T_SLVV_64 is
+ variable Result : T_SLVV_64(slvv'range);
+ begin
+ for i in slvv'low to slvv'high loop
+ Result(slvv'high - i) := slvv(i);
+ end loop;
+ return Result;
+ end function;
+
+ function rev(slvv : T_SLVV_128) return T_SLVV_128 is
+ variable Result : T_SLVV_128(slvv'range);
+ begin
+ for i in slvv'low to slvv'high loop
+ Result(slvv'high - i) := slvv(i);
+ end loop;
+ return Result;
+ end function;
+
+ function rev(slvv : T_SLVV_256) return T_SLVV_256 is
+ variable Result : T_SLVV_256(slvv'range);
+ begin
+ for i in slvv'low to slvv'high loop
+ Result(slvv'high - i) := slvv(i);
+ end loop;
+ return Result;
+ end function;
+
+ function rev(slvv : T_SLVV_512) return T_SLVV_512 is
+ variable Result : T_SLVV_512(slvv'range);
+ begin
+ for i in slvv'low to slvv'high loop
+ Result(slvv'high - i) := slvv(i);
+ end loop;
+ return Result;
+ end function;
+
+ -- Resize functions
+ -- ==========================================================================
+ -- Resizes the vector to the specified length. Input vectors larger than the specified size are truncated from the left side. Smaller input
+ -- vectors are extended on the left by the provided fill value (default: '0'). Use the resize functions of the numeric_std package for
+ -- value-preserving resizes of the signed and unsigned data types.
+ function resize(slm : T_SLM; size : POSITIVE) return T_SLM is
+ variable Result : T_SLM(size - 1 downto 0, slm'high(2) downto slm'low(2)) := (others => (others => '0'));
+ begin
+ for i in slm'range(1) loop
+ for j in slm'high(2) downto slm'low(2) loop
+ Result(i, j) := slm(i, j);
+ end loop;
+ end loop;
+ return Result;
+ end function;
+
+ function to_string(slvv : T_SLVV_8; sep : CHARACTER := ':') return STRING is
+ constant hex_len : POSITIVE := ite((sep = C_POC_NUL), (slvv'length * 2), (slvv'length * 3) - 1);
+ variable Result : STRING(1 to hex_len) := (others => sep);
+ variable pos : POSITIVE := 1;
+ begin
+ for i in slvv'range loop
+ Result(pos to pos + 1) := to_string(slvv(i), 'h');
+ pos := pos + ite((sep = C_POC_NUL), 2, 3);
+ end loop;
+ return Result;
+ end function;
+
+ function to_string_bin(slm : T_SLM; groups : POSITIVE := 4; format : CHARACTER := 'h') return STRING is
+ variable PerLineOverheader : POSITIVE := div_ceil(slm'length(2), groups);
+ variable Result : STRING(1 to (slm'length(1) * (slm'length(2) + PerLineOverheader)) + 10);
+ variable Writer : POSITIVE;
+ variable GroupCounter : NATURAL;
+ begin
+ Result := (others => C_POC_NUL);
+ Result(1) := LF;
+ Writer := 2;
+ GroupCounter := 0;
+ for i in slm'low(1) to slm'high(1) loop
+ for j in slm'high(2) downto slm'low(2) loop
+ Result(Writer) := to_char(slm(i, j));
+ Writer := Writer + 1;
+ GroupCounter := GroupCounter + 1;
+ if (GroupCounter = groups) then
+ Result(Writer) := ' ';
+ Writer := Writer + 1;
+ GroupCounter := 0;
+ end if;
+ end loop;
+ Result(Writer - 1) := LF;
+ GroupCounter := 0;
+ end loop;
+ return str_trim(Result);
+ end function;
+
+ function to_string(slm : T_SLM; groups : POSITIVE := 4; format : CHARACTER := 'b') return STRING is
+ begin
+ if (format = 'b') then
+ return to_string_bin(slm, groups);
+ else
+ return "Format not supported.";
+ end if;
+ end function;
+end package body;
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