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| author | Tristan Gingold <tgingold@free.fr> | 2019-07-25 06:10:38 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-07-25 06:10:38 +0200 |
| commit | f992c33f302b0e5060d30dedff94ee9fa15190ef (patch) | |
| tree | e114467749e011cf29454483b9bc93a3a8a09f35 | |
| parent | 8d8e3fd40444b7f8c11e6ff510d1fbf70b7954af (diff) | |
| download | ghdl-f992c33f302b0e5060d30dedff94ee9fa15190ef.tar.gz ghdl-f992c33f302b0e5060d30dedff94ee9fa15190ef.tar.bz2 ghdl-f992c33f302b0e5060d30dedff94ee9fa15190ef.zip | |
vhdl+synth: recognize /= to std_logic_unsigned.
| -rw-r--r-- | src/synth/synth-expr.adb | 3 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_unsigned.adb | 8 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 6 |
3 files changed, 16 insertions, 1 deletions
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index 01b5ac649..5ace33ed3 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -813,6 +813,9 @@ package body Synth.Expr is | Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Slv_Slv => -- "=" (Unsigned, Unsigned) [resize] return Synth_Compare_Uns_Uns (Id_Eq); + when Iir_Predefined_Ieee_Std_Logic_Unsigned_Ne_Slv_Slv => + -- "/=" (Unsigned, Unsigned) [resize] + return Synth_Compare_Uns_Uns (Id_Ne); when Iir_Predefined_Ieee_Numeric_Std_Ne_Uns_Nat => -- "/=" (Unsigned, Natural) return Synth_Compare_Uns_Nat (Id_Ne); diff --git a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb index 5acf9ae4f..dafbf7dad 100644 --- a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb +++ b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb @@ -33,6 +33,12 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Int_Slv, others => Iir_Predefined_None); + Ne_Patterns : constant Binary_Pattern_Type := + (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Ne_Slv_Slv, + Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Unsigned_Ne_Slv_Int, + Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Ne_Int_Slv, + others => Iir_Predefined_None); + Lt_Patterns : constant Binary_Pattern_Type := (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Slv_Slv, Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Slv_Int, @@ -126,6 +132,8 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is case Get_Identifier (Decl) is when Name_Op_Equality => Handle_Binary (Eq_Patterns); + when Name_Op_Inequality => + Handle_Binary (Ne_Patterns); when Name_Op_Less => Handle_Binary (Lt_Patterns); when Name_Op_Less_Equal => diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 6930d79bc..57c6bb73c 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -4980,7 +4980,11 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Slv_Slv, Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Slv_Int, - Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Int_Slv + Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Int_Slv, + + Iir_Predefined_Ieee_Std_Logic_Unsigned_Ne_Slv_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Ne_Slv_Int, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Ne_Int_Slv ); -- Return TRUE iff FUNC is a short-cut predefined function. |