Add reproducer for #332

8 files changed, 513 insertions, 0 deletions

diff --git a/testsuite/gna/issue332/comp.bat b/testsuite/gna/issue332/comp.bat
new file mode 100644
index 000000000..73f9ea93c
--- /dev/null
+++ b/testsuite/gna/issue332/comp.bat
@@ -0,0 +1,6 @@
+ghdl -a -fexplicit -frelaxed-rules --mb-comments --warn-binding --ieee=synopsys --no-vital-checks --std=08 ilos_sim_pkg.vhd

+ghdl -a -fexplicit -frelaxed-rules --mb-comments --warn-binding --ieee=synopsys --no-vital-checks --std=08 irqc_pif_pkg.vhd

+ghdl -a -fexplicit -frelaxed-rules --mb-comments --warn-binding --ieee=synopsys --no-vital-checks --std=08 irqc_pif.vhd

+ghdl -a -fexplicit -frelaxed-rules --mb-comments --warn-binding --ieee=synopsys --no-vital-checks --std=08 irqc_tb.vhd

+ghdl -r -fexplicit -frelaxed-rules --mb-comments --warn-binding --ieee=synopsys --no-vital-checks --std=08 tb_irqc --wave=sim.ghw

+rem ghdl -r -fexplicit -frelaxed-rules --mb-comments --warn-binding --ieee=synopsys --no-vital-checks --std=08 tb_irqc --vcd=sim.vcd
\ No newline at end of file
diff --git a/testsuite/gna/issue332/ilos_sim_pkg.vhd b/testsuite/gna/issue332/ilos_sim_pkg.vhd
new file mode 100644
index 000000000..68f216a1d
--- /dev/null
+++ b/testsuite/gna/issue332/ilos_sim_pkg.vhd
@@ -0,0 +1,49 @@
+

+Library ieee;

+use ieee.std_logic_1164.all;

+use ieee.numeric_std.all;

+

+package ilos_sim_pkg is

+

+procedure clk_gen(

+	signal clk : out std_logic; 

+	constant FREQ : real; PHASE : time := 0 fs; 

+	signal run : std_logic

+	);

+

+end package ilos_sim_pkg;

+

+

+package body ilos_sim_pkg is

+

+-- Advanced procedure for clock generation, with period adjust to match frequency over time, and run control by signal

+procedure clk_gen(signal clk : out std_logic; constant FREQ : real; PHASE : time := 0 fs; signal run : std_logic) is

+  constant HIGH_TIME   : time := 0.5 sec / FREQ;  -- High time as fixed value

+  variable low_time_v  : time;                    -- Low time calculated per cycle; always >= HIGH_TIME

+  variable cycles_v    : real := 0.0;             -- Number of cycles

+  variable freq_time_v : time := 0 fs;            -- Time used for generation of cycles

+begin

+  -- Check the arguments

+  assert (HIGH_TIME /= 0 fs) report "clk_gen: High time is zero; time resolution to large for frequency" severity FAILURE;

+  -- Initial phase shift

+  clk <= '0';

+  wait for PHASE;

+  -- Generate cycles

+  loop

+    -- Only high pulse if run is '1' or 'H'

+    if (run = '1') or (run = 'H') then

+      clk <= run;

+    end if;

+    wait for HIGH_TIME;

+    -- Low part of cycle

+    clk <= '0';

+    low_time_v := 1 sec * ((cycles_v + 1.0) / FREQ) - freq_time_v - HIGH_TIME;  -- + 1.0 for cycle after current

+    wait for low_time_v;

+    -- Cycle counter and time passed update

+    cycles_v := cycles_v + 1.0;

+    freq_time_v := freq_time_v + HIGH_TIME + low_time_v;

+  end loop;

+end procedure;

+

+

+end package body ilos_sim_pkg;
\ No newline at end of file
diff --git a/testsuite/gna/issue332/irqc_pif.vhd b/testsuite/gna/issue332/irqc_pif.vhd
new file mode 100644
index 000000000..91121e2c8
--- /dev/null
+++ b/testsuite/gna/issue332/irqc_pif.vhd
@@ -0,0 +1,121 @@
+--========================================================================================================================
+-- Copyright (c) 2016 by Bitvis AS.  All rights reserved.
+-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not, 
+-- contact Bitvis AS <support@bitvis.no>.
+--
+-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
+-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
+--========================================================================================================================
+
+------------------------------------------------------------------------------------------
+-- VHDL unit     : Bitvis IRQC Library : irqc_pif
+--
+-- Description   : See dedicated powerpoint presentation and README-file(s)
+------------------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.irqc_pif_pkg.all;
+
+entity irqc_pif is
+  port(
+    arst : in  std_logic;
+    clk  : in  std_logic;
+    -- CPU interface
+    cs   : in  std_logic;
+    addr : in  unsigned;
+    wr   : in  std_logic;
+    rd   : in  std_logic;
+    din  : in  std_logic_vector(7 downto 0);
+    dout : out std_logic_vector(7 downto 0)   := (others => '0');
+    --
+    p2c  : out t_p2c;
+    c2p  : in  t_c2p
+  );
+end irqc_pif;
+
+architecture rtl of irqc_pif is
+  signal p2c_i : t_p2c;   -- internal version of output
+  signal dout_i : std_logic_vector(7 downto 0) := (others => '0');
+
+
+begin
+
+  -- Assigning internally used signals to outputs
+  p2c <= p2c_i;
+
+
+  p_read_reg : process(cs, addr, rd, c2p, p2c_i)
+  begin
+    -- default values
+    dout_i               <= (others => '0');
+
+    if cs = '1' and rd = '1' then
+      case to_integer(addr) is
+        when C_ADDR_IRR =>
+          dout_i(C_NUM_SOURCES-1 downto 0) <= c2p.aro_irr;
+        when C_ADDR_IER =>
+          dout_i(C_NUM_SOURCES-1 downto 0) <= p2c_i.rw_ier;
+        when C_ADDR_IPR =>
+          dout_i(C_NUM_SOURCES-1 downto 0) <= c2p.aro_ipr;
+        when C_ADDR_IRQ2CPU_ALLOWED =>
+          dout_i(0)                        <= c2p.aro_irq2cpu_allowed;
+        when others =>
+          null;
+      end case;
+    end if;
+
+  end process p_read_reg;
+
+  dout <= dout_i;
+
+  -- Writing to registers that are not functionally manipulated
+  p_write_reg : process(clk, arst)
+  begin
+    if arst = '1' then
+      p2c_i.rw_ier       <= (others => '0');
+
+    elsif rising_edge(clk) then
+      if cs = '1' and wr = '1' then
+        case to_integer(addr) is
+          when C_ADDR_IER =>
+            p2c_i.rw_ier <= din(C_NUM_SOURCES-1 downto 0);
+          -- Auxiliary write (below)
+          when others     =>
+            null;
+        end case;
+      end if;
+    end if;
+  end process p_write_reg;
+
+  -- Writing to registers that are functionally manipulated and/or located outside PIF (or dummy registers)
+  p_aux : process(wr, addr, din)
+  begin
+    -- Note that arst is not considered here, but must be considered in any clocked process in the core
+    -- Default - always to return to these values
+    p2c_i.awt_icr(C_NUM_SOURCES-1 downto 0)  <= (others => '0');
+    p2c_i.awt_itr(C_NUM_SOURCES-1 downto 0)  <= (others => '0');
+    p2c_i.awt_irq2cpu_ena                    <= '0';
+    p2c_i.awt_irq2cpu_disable                <= '0';
+
+    if (cs = '1' and wr = '1') then
+      case to_integer(addr) is
+        when C_ADDR_ITR =>
+          p2c_i.awt_itr         <= din(C_NUM_SOURCES-1 downto 0);
+        when C_ADDR_ICR =>
+          p2c_i.awt_icr         <= din(C_NUM_SOURCES-1 downto 0);
+        when C_ADDR_IRQ2CPU_ENA =>
+          p2c_i.awt_irq2cpu_ena <= din(0);
+        when C_ADDR_IRQ2CPU_DISABLE =>
+          p2c_i.awt_irq2cpu_disable <= din(0);
+        when others =>
+          null;
+      end case;
+    end if;
+  end process p_aux;
+
+end rtl;
diff --git a/testsuite/gna/issue332/irqc_pif_pkg.vhd b/testsuite/gna/issue332/irqc_pif_pkg.vhd
new file mode 100644
index 000000000..34bd72509
--- /dev/null
+++ b/testsuite/gna/issue332/irqc_pif_pkg.vhd
@@ -0,0 +1,110 @@
+--========================================================================================================================
+-- Copyright (c) 2016 by Bitvis AS.  All rights reserved.
+-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not, 
+-- contact Bitvis AS <support@bitvis.no>.
+--
+-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
+-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
+--========================================================================================================================
+
+------------------------------------------------------------------------------------------
+-- VHDL unit     : Bitvis IRQC Library : irqc_pif_pkg
+--
+-- Description   : See dedicated powerpoint presentation and README-file(s)
+------------------------------------------------------------------------------------------
+
+
+Library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package irqc_pif_pkg is
+
+  -- Change this to a generic when generic in packages is allowed (VHDL 2008)
+  constant C_NUM_SOURCES : integer := 6;  --  1 <= C_NUM_SOURCES <= Data width
+
+  -- Notation for regs: (Included in constant name as info to SW)
+  -- - RW: Readable and writable reg.
+  -- - RO: Read only reg. (output from IP)
+  -- - WO: Write only reg. (typically single cycle strobe to IP)
+
+  -- Notation for signals (or fields in record) going between PIF and core:
+  -- Same notations as for register-constants above, but
+  -- a preceeding 'a' (e.g. awo) means the register is auxiliary to the PIF.
+  -- This means no flop in the PIF, but in the core. (Or just a dummy-register with no flop)
+
+  constant C_ADDR_IRR             : integer := 0;
+  constant C_ADDR_IER             : integer := 1;
+  constant C_ADDR_ITR             : integer := 2;
+  constant C_ADDR_ICR             : integer := 3;
+  constant C_ADDR_IPR             : integer := 4;
+  constant C_ADDR_IRQ2CPU_ENA     : integer := 5;
+  constant C_ADDR_IRQ2CPU_DISABLE : integer := 6;
+  constant C_ADDR_IRQ2CPU_ALLOWED : integer := 7;
+
+  -- Signals from pif to core
+  type t_p2c is record
+    rw_ier               : std_logic_vector(C_NUM_SOURCES-1 downto 0);
+    awt_itr              : std_logic_vector(C_NUM_SOURCES-1 downto 0);
+    awt_icr              : std_logic_vector(C_NUM_SOURCES-1 downto 0);
+    awt_irq2cpu_ena      : std_logic;
+    awt_irq2cpu_disable  : std_logic;
+  end record t_p2c;
+
+  -- Signals from core to PIF
+  type t_c2p is record
+    aro_irr              : std_logic_vector(C_NUM_SOURCES-1 downto 0);
+    aro_ipr              : std_logic_vector(C_NUM_SOURCES-1 downto 0);
+    aro_irq2cpu_allowed  : std_logic;
+  end record t_c2p;
+  
+  type t_sbi_if is record
+    cs      : std_logic;          -- to dut
+    addr    : unsigned;           -- to dut
+    rd      : std_logic;          -- to dut
+    wr      : std_logic;          -- to dut
+    wdata   : std_logic_vector;   -- to dut
+    ready   : std_logic;          -- from dut
+    rdata   : std_logic_vector;   -- from dut
+  end record;
+  
+    ------------------------------------------
+  -- init_sbi_if_signals
+  ------------------------------------------
+  -- - This function returns an SBI interface with initialized signals.
+  -- - All SBI input signals are initialized to 0
+  -- - All SBI output signals are initialized to Z
+  function init_sbi_if_signals(
+    addr_width : natural;
+    data_width : natural
+    ) return t_sbi_if;
+	
+
+end package irqc_pif_pkg;
+
+package body irqc_pif_pkg is
+
+  ---------------------------------------------------------------------------------
+  -- initialize sbi to dut signals
+  ---------------------------------------------------------------------------------
+
+  function init_sbi_if_signals(
+    addr_width : natural;
+    data_width : natural
+    ) return t_sbi_if is
+    variable result : t_sbi_if( addr(addr_width - 1 downto 0), 
+                                wdata(data_width - 1 downto 0), 
+                                rdata(data_width - 1 downto 0));
+  begin
+    result.cs     := '0';
+    result.rd     := '0';
+    result.wr     := '0';
+    result.addr   := (others => '0');
+    result.wdata  := (others => '0');
+    result.ready  := 'Z';
+    result.rdata  := (others => 'Z');
+    return result;
+  end function;
+end package body irqc_pif_pkg;
diff --git a/testsuite/gna/issue332/irqc_tb.vhd b/testsuite/gna/issue332/irqc_tb.vhd
new file mode 100644
index 000000000..2b085fd07
--- /dev/null
+++ b/testsuite/gna/issue332/irqc_tb.vhd
@@ -0,0 +1,134 @@
+--********************************************************************************************************************--
+--! @brief Testbench for decoder simulator
+--********************************************************************************************************************--
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library STD;
+use std.env.all; 
+
+use work.irqc_pif_pkg.all;
+use work.ilos_sim_pkg.all;
+
+--! Local libraries
+library work;
+
+--! Entity/Package Description
+entity tb_irqc is
+end entity tb_irqc;
+
+architecture tb of tb_irqc is
+
+-- Signal declarations
+SIGNAL arst_sig: 	std_logic;
+SIGNAL clk_sig: 	std_logic;
+SIGNAL cs_sig: 		std_logic;
+SIGNAL addr_sig: 	unsigned(2 DOWNTO 0);
+SIGNAL wr_sig: 		std_logic;
+SIGNAL rd_sig: 		std_logic;
+SIGNAL din_sig: 	std_logic_vector(7 DOWNTO 0);
+SIGNAL dout_sig: 	std_logic_vector(7 DOWNTO 0);
+SIGNAL p2c_sig: 	t_p2c;
+SIGNAL c2p_sig: 	t_c2p;
+SIGNAL run_sig:		std_logic;
+
+signal sbi_if : t_sbi_if(addr(2 downto 0), wdata(7 downto 0), rdata(7 downto 0)) := init_sbi_if_signals(3, 8);
+ 
+
+--! Component declaration for Behavioral Decoder
+
+COMPONENT irqc_pif IS
+  PORT(
+    arst : in  std_logic;
+    clk  : in  std_logic;
+    -- CPU interface
+    cs   : in  std_logic;
+    addr : in  unsigned;
+    wr   : in  std_logic;
+    rd   : in  std_logic;
+    din  : in  std_logic_vector(7 downto 0);
+    dout : out std_logic_vector(7 downto 0)   := (others => '0');
+    --
+    p2c  : out t_p2c;
+    c2p  : in  t_c2p
+  );
+END COMPONENT irqc_pif;

+
+BEGIN
+
+
+IRQC: irqc_pif PORT MAP (
+	arst => arst_sig,
+	clk  => clk_sig,
+	cs   => cs_sig,
+	addr => addr_sig,
+	wr   => wr_sig, 
+	rd   => rd_sig, 
+	din  => din_sig,
+	dout => dout_sig,
+	p2c  => p2c_sig,
+	c2p  => c2p_sig
+);
+	
+-- Clock generation with concurrent procedure call
+clk_gen(clk_sig, 50.0E6, 0 fs, run_sig);  -- 50 MHz clock
+
+-- Time resolution show
+-- assert FALSE report "Time resolution: " & time'image(time'succ(0 fs)) severity NOTE;
+
+

+tb: PROCESS

+BEGIN	
+	run_sig <= '1';
+	arst_sig <= '1';
+	
+	cs_sig <= '0';
+	addr_sig <= to_unsigned(0, addr_sig'length);
+	wr_sig <= '0';
+	rd_sig <= '0';
+	din_sig <= (others => '0');
+	c2p_sig.aro_irr <= (others => '0');
+	c2p_sig.aro_ipr <= (others => '0');
+	c2p_sig.aro_irq2cpu_allowed <= '0';
+
+	wait for 200 ns;
+	arst_sig <= '0';
+	
+	wait for 205 nS;
+	rd_sig <= '1';
+	cs_sig <= '1';
+	
+	wait for 20 ns;
+	addr_sig <= to_unsigned(C_ADDR_IER, addr_sig'length);
+	wait for 20 nS;
+	addr_sig <= to_unsigned(C_ADDR_IPR, addr_sig'length);
+	wait for 20 nS;
+	addr_sig <= to_unsigned(C_ADDR_IRQ2CPU_ALLOWED, addr_sig'length);
+	wait for 20 nS;
+	addr_sig <= to_unsigned(C_ADDR_IER, addr_sig'length);
+	din_sig <= X"15";
+	wr_sig <= '1';
+	rd_sig <= '0';
+	wait for 20 ns;
+	cs_sig <= '0';
+	wr_sig <= '0';
+	rd_sig <= '1';
+	cs_sig <= '1';
+	wait for 80 ns;
+	
+	
+	cs_sig <= '0';
+	rd_sig <= '0';
+	wait for 200 nS;
+	
+	-- End simulation

+	run_sig <= '0';
+	wait for 200 nS;
+	finish;

+	

+	

+END PROCESS tb;

+

+	
+end architecture tb;

diff --git a/testsuite/gna/issue332/repro_rec.vhdl b/testsuite/gna/issue332/repro_rec.vhdl
new file mode 100644
index 000000000..3f04d3b92
--- /dev/null
+++ b/testsuite/gna/issue332/repro_rec.vhdl
@@ -0,0 +1,33 @@
+entity repro_rec is
+end;
+
+architecture behav of repro_rec is
+  type my_rec is record
+    s : natural;
+    b : bit_vector;
+    c : bit_vector;
+  end record;
+
+  subtype my_rec1 is my_rec (c (2 to 3));
+  
+  signal r : my_rec1 (b (1 to 3));
+  signal a : bit_vector (0 to 1);
+begin
+  process
+  begin
+    r.s <= 1;
+    r.b <= "010";
+    wait for 1 ns;
+    r.b <= "101";
+    wait;
+  end process;
+
+  blk: block
+    port (a1 : bit_vector);
+    port map (a1 => a);
+  begin
+  end block;
+  
+end;
+
+    
diff --git a/testsuite/gna/issue332/repro_rec2.vhdl b/testsuite/gna/issue332/repro_rec2.vhdl
new file mode 100644
index 000000000..fede4eda5
--- /dev/null
+++ b/testsuite/gna/issue332/repro_rec2.vhdl
@@ -0,0 +1,30 @@
+entity repro_rec is
+end;
+
+architecture behav of repro_rec is
+  type my_rec is record
+    s : natural;
+    b : bit_vector;
+  end record;
+
+  signal r : my_rec (b (1 to 3));
+  signal a : bit_vector (0 to 1);
+begin
+  process
+  begin
+    r.s <= 1;
+    r.b <= "010";
+    wait for 1 ns;
+    r.b <= "101";
+    wait;
+  end process;
+
+  blk: block
+    port (r1: my_rec; a1 : bit_vector);
+    port map (r1 => r, a1 => a);
+  begin
+  end block;
+  
+end;
+
+    
diff --git a/testsuite/gna/issue332/testsuite.sh b/testsuite/gna/issue332/testsuite.sh
new file mode 100755
index 000000000..1dfe7cd21
--- /dev/null
+++ b/testsuite/gna/issue332/testsuite.sh
@@ -0,0 +1,30 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=" -fexplicit -frelaxed-rules --mb-comments --warn-binding --ieee=synopsys --no-vital-checks --std=08"
+
+analyze ilos_sim_pkg.vhd
+analyze irqc_pif_pkg.vhd
+analyze irqc_pif.vhd
+analyze irqc_tb.vhd
+elab tb_irqc
+
+if ghdl_has_feature tb_irqc ghw; then
+  simulate tb_irqc --wave=sim.ghw
+fi
+
+analyze repro_rec.vhdl
+elab repro_rec
+
+if ghdl_has_feature repro_rec ghw; then
+  simulate repro_rec --wave=rec.ghw
+fi
+
+clean
+if [ $# -eq 0 ]; then
+  rm -f rec.ghw sim.ghw
+fi
+
+
+echo "Test successful"