ieee: recognize ieee.numeric_std.

12 files changed, 407 insertions, 41 deletions

diff --git a/src/std_names.adb b/src/std_names.adb
index 5e8e4bae2..8993caf17 100644
--- a/src/std_names.adb
+++ b/src/std_names.adb
@@ -410,6 +410,12 @@ package body Std_Names is
       Def ("vital_timing",       Name_VITAL_Timing);
       Def ("vital_level0",       Name_VITAL_Level0);
       Def ("vital_level1",       Name_VITAL_Level1);
+      Def ("numeric_std",        Name_Numeric_Std);
+      Def ("numeric_bit",        Name_Numeric_Bit);
+      Def ("unsigned",           Name_Unsigned);
+      Def ("signed",             Name_Signed);
+      Def ("unresolved_unsigned", Name_Unresolved_Unsigned);
+      Def ("unresolved_signed",  Name_Unresolved_Signed);
       Def ("std_logic_arith",    Name_Std_Logic_Arith);
       Def ("std_logic_signed",   Name_Std_Logic_Signed);
       Def ("std_logic_textio",   Name_Std_Logic_Textio);
diff --git a/src/std_names.ads b/src/std_names.ads
index 70badeb34..a5566b0c7 100644
--- a/src/std_names.ads
+++ b/src/std_names.ads
@@ -482,10 +482,16 @@ package Std_Names is
    Name_VITAL_Timing       : constant Name_Id := Name_First_Ieee + 008;
    Name_VITAL_Level0       : constant Name_Id := Name_First_Ieee + 009;
    Name_VITAL_Level1       : constant Name_Id := Name_First_Ieee + 010;
-   Name_Std_Logic_Arith    : constant Name_Id := Name_First_Ieee + 011;
-   Name_Std_Logic_Signed   : constant Name_Id := Name_First_Ieee + 012;
-   Name_Std_Logic_Textio   : constant Name_Id := Name_First_Ieee + 013;
-   Name_Std_Logic_Unsigned : constant Name_Id := Name_First_Ieee + 014;
+   Name_Numeric_Std        : constant Name_Id := Name_First_Ieee + 011;
+   Name_Numeric_Bit        : constant Name_Id := Name_First_Ieee + 012;
+   Name_Unsigned           : constant Name_Id := Name_First_Ieee + 013;
+   Name_Signed             : constant Name_Id := Name_First_Ieee + 014;
+   Name_Unresolved_Unsigned : constant Name_Id := Name_First_Ieee + 015;
+   Name_Unresolved_Signed  : constant Name_Id := Name_First_Ieee + 016;
+   Name_Std_Logic_Arith    : constant Name_Id := Name_First_Ieee + 017;
+   Name_Std_Logic_Signed   : constant Name_Id := Name_First_Ieee + 018;
+   Name_Std_Logic_Textio   : constant Name_Id := Name_First_Ieee + 019;
+   Name_Std_Logic_Unsigned : constant Name_Id := Name_First_Ieee + 020;
    Name_Last_Ieee          : constant Name_Id := Name_Std_Logic_Unsigned;
 
    --  Verilog keywords.
diff --git a/src/vhdl/canon.ads b/src/vhdl/canon.ads
index 869755472..7ae2579f6 100644
--- a/src/vhdl/canon.ads
+++ b/src/vhdl/canon.ads
@@ -18,8 +18,7 @@
 with Iirs; use Iirs;
 
 package Canon is
-   --  If true, a label will be added for statements which do not have a
-   --  label.
+   --  If true, a label will be added to unlabelled concurrent statements.
    Canon_Flag_Add_Labels : Boolean := False;
 
    --  If true, canon sequentials statements (processes and subprograms).
diff --git a/src/vhdl/ieee-numeric.adb b/src/vhdl/ieee-numeric.adb
new file mode 100644
index 000000000..d87cb1898
--- /dev/null
+++ b/src/vhdl/ieee-numeric.adb
@@ -0,0 +1,259 @@
+--  Nodes recognizer for ieee.numeric_std and ieee.numeric_bit.
+--  Copyright (C) 2016 Tristan Gingold
+--
+--  GHDL is free software; you can redistribute it and/or modify it under
+--  the terms of the GNU General Public License as published by the Free
+--  Software Foundation; either version 2, or (at your option) any later
+--  version.
+--
+--  GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
+--  WARRANTY; without even the implied warranty of MERCHANTABILITY or
+--  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+--  for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with GHDL; see the file COPYING.  If not, write to the Free
+--  Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+--  02111-1307, USA.
+
+with Types; use Types;
+with Std_Package;
+with Std_Names; use Std_Names;
+with Errorout; use Errorout;
+with Ieee.Std_Logic_1164;
+
+package body Ieee.Numeric is
+   type Pkg_Kind is (Pkg_Std, Pkg_Bit);
+   type Sign_Kind is (Type_Signed, Type_Unsigned,
+                      Type_Log, Type_Slv, Type_Suv);
+   subtype Sign_Num_Kind is Sign_Kind range Type_Signed .. Type_Unsigned;
+   type Arg_Kind is (Arg_Vect, Arg_Scal);
+   type Args_Kind is (Arg_Vect_Vect, Arg_Vect_Scal, Arg_Scal_Vect,
+                      Arg_Vect_Log, Arg_Log_Vect);
+
+   type Binary_Pattern_Type is array (Pkg_Kind, Sign_Num_Kind, Args_Kind)
+     of Iir_Predefined_Functions;
+
+   Add_Patterns : constant Binary_Pattern_Type :=
+     (Pkg_Std =>
+        (Type_Unsigned =>
+           (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Uns,
+            Arg_Vect_Scal => Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Nat,
+            Arg_Scal_Vect => Iir_Predefined_Ieee_Numeric_Std_Add_Nat_Uns,
+            Arg_Vect_Log  => Iir_Predefined_None,
+            Arg_Log_Vect  => Iir_Predefined_None),
+         Type_Signed =>
+           (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Sgn,
+            Arg_Vect_Scal => Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Int,
+            Arg_Scal_Vect => Iir_Predefined_Ieee_Numeric_Std_Add_Int_Sgn,
+            Arg_Vect_Log  => Iir_Predefined_None,
+            Arg_Log_Vect  => Iir_Predefined_None)),
+      Pkg_Bit =>
+        (others =>
+           (others => Iir_Predefined_None)));
+
+   Eq_Patterns : constant Binary_Pattern_Type :=
+     (Pkg_Std =>
+        (Type_Unsigned =>
+           (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Eq_Uns_Uns,
+            Arg_Vect_Scal => Iir_Predefined_Ieee_Numeric_Std_Eq_Uns_Nat,
+            Arg_Scal_Vect => Iir_Predefined_Ieee_Numeric_Std_Eq_Nat_Uns,
+            Arg_Vect_Log  => Iir_Predefined_None,
+            Arg_Log_Vect  => Iir_Predefined_None),
+         Type_Signed =>
+           (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Eq_Sgn_Sgn,
+            Arg_Vect_Scal => Iir_Predefined_Ieee_Numeric_Std_Eq_Sgn_Int,
+            Arg_Scal_Vect => Iir_Predefined_Ieee_Numeric_Std_Eq_Int_Sgn,
+            Arg_Vect_Log  => Iir_Predefined_None,
+            Arg_Log_Vect  => Iir_Predefined_None)),
+      Pkg_Bit =>
+        (others =>
+           (others => Iir_Predefined_None)));
+
+   Error : exception;
+
+   procedure Extract_Declarations (Pkg_Decl : Iir_Package_Declaration;
+                                   Pkg : Pkg_Kind;
+                                   Unsigned_Type : out Iir;
+                                   Signed_Type : out Iir)
+   is
+      procedure Classify_Arg
+        (Arg : Iir; Sign : out Sign_Kind; Kind : out Arg_Kind)
+      is
+         Arg_Type : constant Iir := Get_Type (Arg);
+      begin
+         if Arg_Type = Signed_Type then
+            Sign := Type_Signed;
+            Kind := Arg_Vect;
+         elsif Arg_Type = Unsigned_Type then
+            Sign := Type_Unsigned;
+            Kind := Arg_Vect;
+         elsif Arg_Type = Std_Package.Integer_Subtype_Definition then
+            Sign := Type_Signed;
+            Kind := Arg_Scal;
+         elsif Arg_Type = Std_Package.Natural_Subtype_Definition then
+            Sign := Type_Unsigned;
+            Kind := Arg_Scal;
+         elsif Arg_Type = Ieee.Std_Logic_1164.Std_Ulogic_Type then
+            Sign := Type_Log;
+            Kind := Arg_Scal;
+         elsif Arg_Type = Ieee.Std_Logic_1164.Std_Ulogic_Vector_Type then
+            Sign := Type_Suv;
+            Kind := Arg_Vect;
+         elsif Arg_Type = Ieee.Std_Logic_1164.Std_Logic_Type then
+            Sign := Type_Log;
+            Kind := Arg_Scal;
+         elsif Arg_Type = Ieee.Std_Logic_1164.Std_Logic_Vector_Type then
+            Sign := Type_Slv;
+            Kind := Arg_Vect;
+         else
+            raise Error;
+         end if;
+      end Classify_Arg;
+
+      Decl : Iir;
+      Def : Iir;
+
+      Arg1, Arg2 : Iir;
+      Arg1_Sign, Arg2_Sign : Sign_Kind;
+      Arg1_Kind, Arg2_Kind : Arg_Kind;
+
+      procedure Handle_Binary (Pats : Binary_Pattern_Type)
+      is
+         Kind : Args_Kind;
+         Sign : Sign_Kind;
+      begin
+         if Arg1_Sign = Arg2_Sign then
+            Sign := Arg1_Sign;
+            case Arg1_Kind is
+               when Arg_Vect =>
+                  case Arg2_Kind is
+                     when Arg_Vect => Kind := Arg_Vect_Vect;
+                     when Arg_Scal => Kind := Arg_Vect_Scal;
+                  end case;
+               when Arg_Scal =>
+                  case Arg2_Kind is
+                     when Arg_Vect => Kind := Arg_Scal_Vect;
+                     when Arg_Scal => raise Error;
+                  end case;
+            end case;
+         elsif Arg1_Kind = Arg_Vect and Arg2_Sign = Type_Log then
+            Sign := Arg1_Sign;
+            Kind := Arg_Vect_Log;
+         elsif Arg1_Sign = Type_Log and Arg2_Kind = Arg_Vect then
+            Sign := Arg2_Sign;
+            Kind := Arg_Log_Vect;
+         else
+            raise Error;
+         end if;
+
+         Set_Implicit_Definition (Decl, Pats (Pkg, Sign, Kind));
+      end Handle_Binary;
+
+   begin
+      Decl := Get_Declaration_Chain (Pkg_Decl);
+
+      --  Skip a potential copyright constant.
+      if Decl /= Null_Iir
+        and then Get_Kind (Decl) = Iir_Kind_Constant_Declaration
+        and then (Get_Base_Type (Get_Type (Decl))
+                  = Std_Package.String_Type_Definition)
+      then
+         Decl := Get_Chain (Decl);
+      end if;
+
+      --  The first declaration should be type Unsigned or Unresolved_Unsigned
+      if not (Decl /= Null_Iir
+                and then Get_Kind (Decl) = Iir_Kind_Type_Declaration
+                and then (Get_Identifier (Decl) = Name_Unsigned
+                            or else
+                            Get_Identifier (Decl) = Name_Unresolved_Unsigned))
+      then
+         raise Error;
+      end if;
+
+      Def := Get_Type_Definition (Decl);
+      if Get_Kind (Def) /= Iir_Kind_Array_Type_Definition then
+         raise Error;
+      end if;
+      Unsigned_Type := Def;
+
+      --  The second declaration should be type Signed.
+      Decl := Get_Chain (Decl);
+      Decl := Skip_Implicit (Decl);
+      if not (Decl /= Null_Iir
+                and then Get_Kind (Decl) = Iir_Kind_Type_Declaration
+                and then (Get_Identifier (Decl) = Name_Signed
+                            or else
+                            Get_Identifier (Decl) = Name_Unresolved_Signed))
+      then
+         raise Error;
+      end if;
+
+      Def := Get_Type_Definition (Decl);
+      if Get_Kind (Def) /= Iir_Kind_Array_Type_Definition then
+         raise Error;
+      end if;
+      Signed_Type := Def;
+
+      --  For vhdl 2008, skip subtypes
+      Decl := Get_Chain (Decl);
+      Decl := Skip_Implicit (Decl);
+      while Is_Valid (Decl) loop
+         exit when Get_Kind (Decl) /= Iir_Kind_Subtype_Declaration;
+         Decl := Get_Chain (Decl);
+      end loop;
+
+      --  Handle functions.
+      while Is_Valid (Decl) loop
+         case Get_Kind (Decl) is
+            when Iir_Kind_Function_Declaration =>
+               Arg1 := Get_Interface_Declaration_Chain (Decl);
+               if Is_Null (Arg1) then
+                  raise Error;
+               end if;
+
+               Classify_Arg (Arg1, Arg1_Sign, Arg1_Kind);
+               Arg2 := Get_Chain (Arg1);
+               if Is_Valid (Arg2) then
+                  Classify_Arg (Arg2, Arg2_Sign, Arg2_Kind);
+
+                  case Get_Identifier (Decl) is
+                     when Name_Op_Plus =>
+                        Handle_Binary (Add_Patterns);
+                     when Name_Op_Equality =>
+                        Handle_Binary (Eq_Patterns);
+                     when Name_To_Bstring
+                       | Name_To_Ostring
+                       | Name_To_Hstring =>
+                        null;
+                     when others =>
+                        null;
+                  end case;
+               end if;
+
+            when Iir_Kind_Non_Object_Alias_Declaration
+              | Iir_Kind_Procedure_Declaration =>
+               null;
+
+            when others =>
+               raise Error;
+         end case;
+         Decl := Get_Chain (Decl);
+      end loop;
+   end Extract_Declarations;
+
+   procedure Extract_Std_Declarations (Pkg : Iir_Package_Declaration) is
+   begin
+      Numeric_Std_Pkg := Pkg;
+
+      Extract_Declarations
+        (Pkg, Pkg_Std, Numeric_Std_Unsigned_Type, Numeric_Std_Signed_Type);
+   exception
+      when Error =>
+         Error_Msg_Sem (+Pkg, "package ieee.numeric_std is ill-formed");
+         Numeric_Std_Pkg := Null_Iir;
+         Numeric_Std_Unsigned_Type := Null_Iir;
+         Numeric_Std_Signed_Type := Null_Iir;
+   end Extract_Std_Declarations;
+end Ieee.Numeric;
diff --git a/src/vhdl/ieee-numeric.ads b/src/vhdl/ieee-numeric.ads
new file mode 100644
index 000000000..04213bea7
--- /dev/null
+++ b/src/vhdl/ieee-numeric.ads
@@ -0,0 +1,26 @@
+--  Nodes recognizer for ieee.numeric_std and ieee.numeric_bit.
+--  Copyright (C) 2016 Tristan Gingold
+--
+--  GHDL is free software; you can redistribute it and/or modify it under
+--  the terms of the GNU General Public License as published by the Free
+--  Software Foundation; either version 2, or (at your option) any later
+--  version.
+--
+--  GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
+--  WARRANTY; without even the implied warranty of MERCHANTABILITY or
+--  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+--  for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with GHDL; see the file COPYING.  If not, write to the Free
+--  Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+--  02111-1307, USA.
+
+package Ieee.Numeric is
+   Numeric_Std_Pkg : Iir_Package_Declaration := Null_Iir;
+   Numeric_Std_Unsigned_Type : Iir_Array_Type_Definition := Null_Iir;
+   Numeric_Std_Signed_Type : Iir_Array_Type_Definition := Null_Iir;
+
+   --  Extract declarations from PKG (ieee.numeric_std).
+   procedure Extract_Std_Declarations (Pkg : Iir_Package_Declaration);
+end Ieee.Numeric;
diff --git a/src/vhdl/ieee-std_logic_1164.adb b/src/vhdl/ieee-std_logic_1164.adb
index aa6eb4c53..14b8cd625 100644
--- a/src/vhdl/ieee-std_logic_1164.adb
+++ b/src/vhdl/ieee-std_logic_1164.adb
@@ -18,25 +18,9 @@
 with Types; use Types;
 with Name_Table;
 with Std_Names; use Std_Names;
-with Iirs_Utils; use Iirs_Utils;
 with Errorout; use Errorout;
-with Std_Package;
 
 package body Ieee.Std_Logic_1164 is
-   function Skip_Implicit (Decl : Iir) return Iir
-   is
-      Res : Iir;
-   begin
-      Res := Decl;
-      loop
-         exit when Res = Null_Iir;
-         exit when not (Get_Kind (Res) = Iir_Kind_Function_Declaration
-                          and then Is_Implicit_Subprogram (Res));
-         Res := Get_Chain (Res);
-      end loop;
-      return Res;
-   end Skip_Implicit;
-
    function Is_Scalar_Parameter (Inter : Iir) return Boolean is
    begin
       return Get_Base_Type (Get_Type (Inter)) = Std_Ulogic_Type;
@@ -144,13 +128,7 @@ package body Ieee.Std_Logic_1164 is
       Decl := Get_Declaration_Chain (Pkg);
 
       --  Skip a potential copyright constant.
-      if Decl /= Null_Iir
-        and then Get_Kind (Decl) = Iir_Kind_Constant_Declaration
-        and then (Get_Base_Type (Get_Type (Decl))
-                  = Std_Package.String_Type_Definition)
-      then
-         Decl := Get_Chain (Decl);
-      end if;
+      Decl := Skip_Copyright_Notice (Decl);
 
       --  The first declaration should be type std_ulogic.
       if Decl = Null_Iir
diff --git a/src/vhdl/ieee-std_logic_1164.ads b/src/vhdl/ieee-std_logic_1164.ads
index c8d7614cb..8e2a6846c 100644
--- a/src/vhdl/ieee-std_logic_1164.ads
+++ b/src/vhdl/ieee-std_logic_1164.ads
@@ -15,7 +15,6 @@
 --  along with GHDL; see the file COPYING.  If not, write to the Free
 --  Software Foundation, 59 Temple Place - Suite 330, Boston, MA
 --  02111-1307, USA.
-with Iirs; use Iirs;
 
 package Ieee.Std_Logic_1164 is
    --  Nodes corresponding to declarations in the package.
diff --git a/src/vhdl/ieee-vital_timing.ads b/src/vhdl/ieee-vital_timing.ads
index 7abda2eba..59edf35b0 100644
--- a/src/vhdl/ieee-vital_timing.ads
+++ b/src/vhdl/ieee-vital_timing.ads
@@ -15,7 +15,6 @@
 --  along with GHDL; see the file COPYING.  If not, write to the Free
 --  Software Foundation, 59 Temple Place - Suite 330, Boston, MA
 --  02111-1307, USA.
-with Iirs; use Iirs;
 
 package Ieee.Vital_Timing is
    --  Attribute declarations.
diff --git a/src/vhdl/ieee.adb b/src/vhdl/ieee.adb
new file mode 100644
index 000000000..d730bf388
--- /dev/null
+++ b/src/vhdl/ieee.adb
@@ -0,0 +1,50 @@
+--  Nodes recognizer for ieee packages - utilities.
+--  Copyright (C) 2016 Tristan Gingold
+--
+--  GHDL is free software; you can redistribute it and/or modify it under
+--  the terms of the GNU General Public License as published by the Free
+--  Software Foundation; either version 2, or (at your option) any later
+--  version.
+--
+--  GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
+--  WARRANTY; without even the implied warranty of MERCHANTABILITY or
+--  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+--  for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with GHDL; see the file COPYING.  If not, write to the Free
+--  Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+--  02111-1307, USA.
+
+with Iirs_Utils; use Iirs_Utils;
+with Std_Package;
+
+package body Ieee is
+   function Skip_Copyright_Notice (Decl : Iir) return Iir
+   is
+   begin
+      if Decl /= Null_Iir
+        and then Get_Kind (Decl) = Iir_Kind_Constant_Declaration
+        and then (Get_Base_Type (Get_Type (Decl))
+                    = Std_Package.String_Type_Definition)
+      then
+         return Get_Chain (Decl);
+      else
+         return Decl;
+      end if;
+   end Skip_Copyright_Notice;
+
+   function Skip_Implicit (Decl : Iir) return Iir
+   is
+      Res : Iir;
+   begin
+      Res := Decl;
+      loop
+         exit when Res = Null_Iir;
+         exit when not (Get_Kind (Res) = Iir_Kind_Function_Declaration
+                          and then Is_Implicit_Subprogram (Res));
+         Res := Get_Chain (Res);
+      end loop;
+      return Res;
+   end Skip_Implicit;
+end Ieee;
diff --git a/src/vhdl/ieee.ads b/src/vhdl/ieee.ads
index 48ab37630..e29e50f4d 100644
--- a/src/vhdl/ieee.ads
+++ b/src/vhdl/ieee.ads
@@ -1,5 +1,26 @@
---  Top of ieee hierarchy.
---  Too small to be copyrighted.
+--  Nodes recognizer for ieee packages - utilities.
+--  Copyright (C) 2016 Tristan Gingold
+--
+--  GHDL is free software; you can redistribute it and/or modify it under
+--  the terms of the GNU General Public License as published by the Free
+--  Software Foundation; either version 2, or (at your option) any later
+--  version.
+--
+--  GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
+--  WARRANTY; without even the implied warranty of MERCHANTABILITY or
+--  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+--  for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with GHDL; see the file COPYING.  If not, write to the Free
+--  Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+--  02111-1307, USA.
+with Iirs; use Iirs;
+
 package Ieee is
-   pragma Pure (Ieee);
+   --  Skip constant string declaration for a copyright, if present.
+   function Skip_Copyright_Notice (Decl : Iir) return Iir;
+
+   --  Return the next node after implicit subprogram declarations.
+   function Skip_Implicit (Decl : Iir) return Iir;
 end Ieee;
diff --git a/src/vhdl/iirs.ads b/src/vhdl/iirs.ads
index e1a3021bb..a12ee15bb 100644
--- a/src/vhdl/iirs.ads
+++ b/src/vhdl/iirs.ads
@@ -4671,8 +4671,25 @@ package Iirs is
        Iir_Predefined_Ieee_1164_Vector_Nor,
        Iir_Predefined_Ieee_1164_Vector_Xor,
        Iir_Predefined_Ieee_1164_Vector_Xnor,
-       Iir_Predefined_Ieee_1164_Vector_Not
-      );
+       Iir_Predefined_Ieee_1164_Vector_Not,
+
+       --  Numeric_Std.
+       --  Abbreviations:
+       --  Uns: Unsigned, Sgn: Signed, Nat: Natural, Int: Integer.
+       Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Uns,
+       Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Nat,
+       Iir_Predefined_Ieee_Numeric_Std_Add_Nat_Uns,
+       Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Sgn,
+       Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Int,
+       Iir_Predefined_Ieee_Numeric_Std_Add_Int_Sgn,
+
+       Iir_Predefined_Ieee_Numeric_Std_Eq_Uns_Uns,
+       Iir_Predefined_Ieee_Numeric_Std_Eq_Uns_Nat,
+       Iir_Predefined_Ieee_Numeric_Std_Eq_Nat_Uns,
+       Iir_Predefined_Ieee_Numeric_Std_Eq_Sgn_Sgn,
+       Iir_Predefined_Ieee_Numeric_Std_Eq_Sgn_Int,
+       Iir_Predefined_Ieee_Numeric_Std_Eq_Int_Sgn
+);
 
    --  Return TRUE iff FUNC is a short-cut predefined function.
    function Iir_Predefined_Shortcut_P (Func : Iir_Predefined_Functions)
diff --git a/src/vhdl/post_sems.adb b/src/vhdl/post_sems.adb
index 2a45879c0..43e8ec76f 100644
--- a/src/vhdl/post_sems.adb
+++ b/src/vhdl/post_sems.adb
@@ -20,6 +20,7 @@ with Std_Names; use Std_Names;
 with Sem_Specs;
 with Ieee.Std_Logic_1164;
 with Ieee.Vital_Timing;
+with Ieee.Numeric;
 with Flags; use Flags;
 
 package body Post_Sems is
@@ -48,11 +49,16 @@ package body Post_Sems is
       if Get_Identifier (Lib) = Name_Ieee then
          --  This is a unit of IEEE.
          if Get_Kind (Lib_Unit) = Iir_Kind_Package_Declaration then
-            if Id = Name_Std_Logic_1164 then
-               Ieee.Std_Logic_1164.Extract_Declarations (Lib_Unit);
-            elsif Id = Name_VITAL_Timing then
-               Ieee.Vital_Timing.Extract_Declarations (Lib_Unit);
-            end if;
+            case Id is
+               when Name_Std_Logic_1164 =>
+                  Ieee.Std_Logic_1164.Extract_Declarations (Lib_Unit);
+               when Name_VITAL_Timing =>
+                  Ieee.Vital_Timing.Extract_Declarations (Lib_Unit);
+               when Name_Numeric_Std =>
+                  Ieee.Numeric.Extract_Std_Declarations (Lib_Unit);
+               when others =>
+                  null;
+            end case;
          end if;
       end if;