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| author | Tristan Gingold <tgingold@free.fr> | 2019-09-28 08:16:13 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-09-28 08:16:13 +0200 |
| commit | ed614df2af4debb68d6533d74a38ed35f9030e1c (patch) | |
| tree | 26a4c8f37311ea2c7b0bf1daf2a12ef156433749 | |
| parent | 4670aa3c0f4f9be576abba68daa17f2667599524 (diff) | |
| download | ghdl-ed614df2af4debb68d6533d74a38ed35f9030e1c.tar.gz ghdl-ed614df2af4debb68d6533d74a38ed35f9030e1c.tar.bz2 ghdl-ed614df2af4debb68d6533d74a38ed35f9030e1c.zip | |
netlists-disp_vhdl: handle id_edge.
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 6e12f4876..6e2628384 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -773,6 +773,9 @@ package body Netlists.Disp_Vhdl is (" \o0 <= \i1; -- reduce and" & NL, Inst); end if; end; + when Id_Edge => + Disp_Template + (" \o0 <= '1' when rising_edge (\i0) else '0';" & NL, Inst); when Id_Assert => Disp_Template (" \l0: assert \i0 = '1' severity error;" & NL, Inst); |