synth: handle vhdl2008 std_logic_1164, handle anonymous_signal.

5 files changed, 30 insertions, 17 deletions

diff --git a/src/synth/synth-decls.adb b/src/synth/synth-decls.adb
index 34d0c7406..688f67a4e 100644
--- a/src/synth/synth-decls.adb
+++ b/src/synth/synth-decls.adb
@@ -33,6 +33,7 @@ with Vhdl.Annotations; use Vhdl.Annotations;
 package body Synth.Decls is
    procedure Synth_Anonymous_Subtype_Indication
      (Syn_Inst : Synth_Instance_Acc; Atype : Node);
+   pragma Unreferenced (Synth_Anonymous_Subtype_Indication);
 
    procedure Create_Var_Wire
      (Syn_Inst : Synth_Instance_Acc; Decl : Iir; Init : Value_Acc)
@@ -113,8 +114,6 @@ package body Synth.Decls is
             --  The elaboration of an index constraint consists of the
             --  declaration of each of the discrete ranges in the index
             --  constraint in some order that is not defined by the language.
-            Synth_Anonymous_Subtype_Indication
-              (Syn_Inst, Get_Element_Subtype (Atype));
             declare
                St_Indexes : constant Iir_Flist :=
                  Get_Index_Subtype_List (Atype);
@@ -134,7 +133,8 @@ package body Synth.Decls is
             end;
          when Iir_Kind_Integer_Subtype_Definition
            | Iir_Kind_Floating_Subtype_Definition
-           | Iir_Kind_Physical_Subtype_Definition =>
+           | Iir_Kind_Physical_Subtype_Definition
+           | Iir_Kind_Enumeration_Subtype_Definition =>
             declare
                Val : Value_Acc;
             begin
@@ -142,8 +142,6 @@ package body Synth.Decls is
                  (Syn_Inst, Get_Range_Constraint (Atype));
                Create_Object (Syn_Inst, Atype, Unshare (Val, Instance_Pool));
             end;
-         when Iir_Kind_Enumeration_Subtype_Definition =>
-            null;
          when others =>
             Error_Kind ("synth_subtype_indication", Atype);
       end case;
@@ -304,6 +302,9 @@ package body Synth.Decls is
                end if;
                Create_Var_Wire (Syn_Inst, Decl, Init);
             end;
+         when Iir_Kind_Anonymous_Signal_Declaration =>
+            Make_Object (Syn_Inst, Wire_Signal, Decl);
+            Create_Var_Wire (Syn_Inst, Decl, null);
          when Iir_Kind_Procedure_Declaration
            | Iir_Kind_Function_Declaration =>
             --  TODO: elaborate interfaces
diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb
index 3521fd2aa..3f20085b4 100644
--- a/src/synth/synth-stmts.adb
+++ b/src/synth/synth-stmts.adb
@@ -114,7 +114,8 @@ package body Synth.Stmts is
             Synth_Assignment (Syn_Inst, Get_Named_Entity (Target), Val);
          when Iir_Kind_Interface_Signal_Declaration
            | Iir_Kind_Variable_Declaration
-           | Iir_Kind_Signal_Declaration =>
+           | Iir_Kind_Signal_Declaration
+           | Iir_Kind_Anonymous_Signal_Declaration =>
             Synth_Assign (Get_Value (Syn_Inst, Target),
                           Val, Get_Type (Target));
          when Iir_Kind_Aggregate =>
diff --git a/src/synth/synth-types.adb b/src/synth/synth-types.adb
index 87034036e..b197ca570 100644
--- a/src/synth/synth-types.adb
+++ b/src/synth/synth-types.adb
@@ -29,24 +29,35 @@ with Synth.Expr;
 with Vhdl.Annotations; use Vhdl.Annotations;
 
 package body Synth.Types is
-   function Is_Bit_Type (Atype : Iir) return Boolean is
+   function Is_Bit_Type (Atype : Node) return Boolean
+   is
+      Btype : Node;
    begin
-      return Atype = Vhdl.Ieee.Std_Logic_1164.Std_Ulogic_Type
+      if Atype = Vhdl.Ieee.Std_Logic_1164.Std_Ulogic_Type
         or else Atype = Vhdl.Ieee.Std_Logic_1164.Std_Logic_Type
         or else Atype = Vhdl.Std_Package.Boolean_Type_Definition
-        or else Atype = Vhdl.Std_Package.Bit_Type_Definition;
+        or else Atype = Vhdl.Std_Package.Bit_Type_Definition
+      then
+         return True;
+      end if;
+      Btype := Get_Base_Type (Atype);
+      if Btype = Atype then
+         return False;
+      else
+         return Is_Bit_Type (Btype);
+      end if;
    end Is_Bit_Type;
 
-   function Is_Vector_Type (Atype : Iir) return Boolean is
+   function Is_Vector_Type (Atype : Node) return Boolean is
    begin
       return Is_Bit_Type (Get_Element_Subtype (Atype))
         and then Get_Nbr_Dimensions (Atype) = 1;
    end Is_Vector_Type;
 
-   function Get_Width (Syn_Inst : Synth_Instance_Acc; Atype : Iir)
+   function Get_Width (Syn_Inst : Synth_Instance_Acc; Atype : Node)
                       return Width
    is
-      Btype : constant Iir := Get_Base_Type (Atype);
+      Btype : constant Node := Get_Base_Type (Atype);
    begin
       case Get_Kind (Atype) is
          when Iir_Kind_Enumeration_Type_Definition =>
diff --git a/src/synth/synth-types.ads b/src/synth/synth-types.ads
index dfc9aeb15..15b12767d 100644
--- a/src/synth/synth-types.ads
+++ b/src/synth/synth-types.ads
@@ -24,10 +24,10 @@ with Vhdl.Nodes; use Vhdl.Nodes;
 
 package Synth.Types is
    --  All known enumeration type that are translated to a single bit.
-   function Is_Bit_Type (Atype : Iir) return Boolean;
+   function Is_Bit_Type (Atype : Node) return Boolean;
 
-   function Is_Vector_Type (Atype : Iir) return Boolean;
+   function Is_Vector_Type (Atype : Node) return Boolean;
 
-   function Get_Width (Syn_Inst : Synth_Instance_Acc; Atype : Iir)
+   function Get_Width (Syn_Inst : Synth_Instance_Acc; Atype : Node)
                       return Width;
 end Synth.Types;
diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb
index 2feba99f5..0dfe1a67a 100644
--- a/src/vhdl/vhdl-annotations.adb
+++ b/src/vhdl/vhdl-annotations.adb
@@ -312,6 +312,8 @@ package body Vhdl.Annotations is
            | Iir_Kind_Floating_Subtype_Definition
            | Iir_Kind_Enumeration_Subtype_Definition
            | Iir_Kind_Physical_Subtype_Definition =>
+            Annotate_Anonymous_Type_Definition
+              (Block_Info, Get_Base_Type (Def));
             El := Get_Range_Constraint (Def);
             if El /= Null_Iir then
                case Get_Kind (El) is
@@ -336,8 +338,6 @@ package body Vhdl.Annotations is
             if Flag_Synthesis then
                Create_Object_Info (Block_Info, Def);
             end if;
-            Annotate_Anonymous_Type_Definition
-              (Block_Info, Get_Base_Type (Def));
 
          when Iir_Kind_Integer_Type_Definition =>
             Set_Info (Def, new Sim_Info_Type'(Kind => Kind_I64_Type,