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author | Tristan Gingold <tgingold@free.fr> | 2021-10-09 20:56:24 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-10-09 20:56:24 +0200 |
commit | e2f68b93cdc5e1a4a73052ca52f941d4675faca4 (patch) | |
tree | 5750928ea0f54dfa42c672e77bcdccaa3f79f19b | |
parent | 7a6fab44f771aa839fd17645c427d6de4b1d7fce (diff) | |
download | ghdl-e2f68b93cdc5e1a4a73052ca52f941d4675faca4.tar.gz ghdl-e2f68b93cdc5e1a4a73052ca52f941d4675faca4.tar.bz2 ghdl-e2f68b93cdc5e1a4a73052ca52f941d4675faca4.zip |
testsuite/synth: add a test for #1886
-rw-r--r-- | testsuite/synth/issue1886/tb_test.vhdl | 37 | ||||
-rw-r--r-- | testsuite/synth/issue1886/tb_test2.vhdl | 37 | ||||
-rw-r--r-- | testsuite/synth/issue1886/tb_test3.vhdl | 37 | ||||
-rw-r--r-- | testsuite/synth/issue1886/test.vhdl | 27 | ||||
-rw-r--r-- | testsuite/synth/issue1886/test2.vhdl | 23 | ||||
-rw-r--r-- | testsuite/synth/issue1886/test3.vhdl | 21 | ||||
-rwxr-xr-x | testsuite/synth/issue1886/testsuite.sh | 11 |
7 files changed, 193 insertions, 0 deletions
diff --git a/testsuite/synth/issue1886/tb_test.vhdl b/testsuite/synth/issue1886/tb_test.vhdl new file mode 100644 index 000000000..148c67435 --- /dev/null +++ b/testsuite/synth/issue1886/tb_test.vhdl @@ -0,0 +1,37 @@ +entity tb_test is +end tb_test; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_test is + signal crnum_in : std_ulogic_vector(2 downto 0) := "000"; + signal cr_in : std_ulogic_vector(31 downto 0); + signal crf_out : std_ulogic_vector(3 downto 0); +begin + dut: entity work.test + port map (crnum_in, cr_in, crf_out); + + process + begin + cr_in <= x"01234567"; + + crnum_in <= "000"; + wait for 1 ns; + assert crf_out = x"0" severity failure; + + crnum_in <= "001"; + wait for 1 ns; + assert crf_out = x"1" severity failure; + + crnum_in <= "100"; + wait for 1 ns; + assert crf_out = x"4" severity failure; + + crnum_in <= "111"; + wait for 1 ns; + assert crf_out = x"7" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/issue1886/tb_test2.vhdl b/testsuite/synth/issue1886/tb_test2.vhdl new file mode 100644 index 000000000..d639e9a3b --- /dev/null +++ b/testsuite/synth/issue1886/tb_test2.vhdl @@ -0,0 +1,37 @@ +entity tb_test2 is +end; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_test2 is + signal crnum_in : std_ulogic_vector(2 downto 0) := "000"; + signal cr_in : std_ulogic_vector(31 downto 0); + signal crf_out : std_ulogic_vector(3 downto 0); +begin + dut: entity work.test2 + port map (crnum_in, cr_in, crf_out); + + process + begin + cr_in <= x"76543210"; + + crnum_in <= "000"; + wait for 1 ns; + assert crf_out = x"0" severity failure; + + crnum_in <= "001"; + wait for 1 ns; + assert crf_out = x"1" severity failure; + + crnum_in <= "100"; + wait for 1 ns; + assert crf_out = x"4" severity failure; + + crnum_in <= "111"; + wait for 1 ns; + assert crf_out = x"7" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/issue1886/tb_test3.vhdl b/testsuite/synth/issue1886/tb_test3.vhdl new file mode 100644 index 000000000..dea482984 --- /dev/null +++ b/testsuite/synth/issue1886/tb_test3.vhdl @@ -0,0 +1,37 @@ +entity tb_test3 is +end tb_test3; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_test3 is + signal crnum_in : std_ulogic_vector(2 downto 0) := "000"; + signal cr_in : std_ulogic_vector(31 downto 0); + signal crf_out : std_ulogic_vector(3 downto 0); +begin + dut: entity work.test3 + port map (crnum_in, cr_in, crf_out); + + process + begin + cr_in <= x"01234567"; + + crnum_in <= "000"; + wait for 1 ns; + assert crf_out = x"0" severity failure; + + crnum_in <= "001"; + wait for 1 ns; + assert crf_out = x"1" severity failure; + + crnum_in <= "100"; + wait for 1 ns; + assert crf_out = x"4" severity failure; + + crnum_in <= "111"; + wait for 1 ns; + assert crf_out = x"7" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/issue1886/test.vhdl b/testsuite/synth/issue1886/test.vhdl new file mode 100644 index 000000000..ccb690f66 --- /dev/null +++ b/testsuite/synth/issue1886/test.vhdl @@ -0,0 +1,27 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity test is + port ( + crnum_in : in std_ulogic_vector(2 downto 0); + cr_in : in std_ulogic_vector(31 downto 0); + crf_out : out std_ulogic_vector(3 downto 0) + ); +end entity test; + +architecture behaviour of test is +begin + test_0: process(all) + variable crnum : integer; + variable j : integer; + begin + crnum := to_integer(unsigned(crnum_in)); + j := (7 - crnum) * 4; + crf_out <= cr_in(j + 3 downto j); + end process; +end architecture behaviour; + +-- factor = -4 +-- l_add = 31 +-- r_add = 28 --> off = 0 diff --git a/testsuite/synth/issue1886/test2.vhdl b/testsuite/synth/issue1886/test2.vhdl new file mode 100644 index 000000000..c7282d6f6 --- /dev/null +++ b/testsuite/synth/issue1886/test2.vhdl @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity test2 is + port ( + crnum_in : in std_ulogic_vector(2 downto 0); + cr_in : in std_ulogic_vector(31 downto 0); + crf_out : out std_ulogic_vector(3 downto 0) + ); +end entity test2; + +architecture behaviour of test2 is +begin + test_0: process(all) + variable crnum : integer; + variable j : integer; + begin + crnum := to_integer(unsigned(crnum_in)); + j := crnum * 4; + crf_out <= cr_in(j + 3 downto j); + end process; +end architecture behaviour; diff --git a/testsuite/synth/issue1886/test3.vhdl b/testsuite/synth/issue1886/test3.vhdl new file mode 100644 index 000000000..d59fb236c --- /dev/null +++ b/testsuite/synth/issue1886/test3.vhdl @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity test3 is + port ( + crnum_in : in std_ulogic_vector(2 downto 0); + cr_in : in std_ulogic_vector(0 to 31); + crf_out : out std_ulogic_vector(3 downto 0) + ); +end; + +architecture behaviour of test3 is +begin + test_0: process(all) + variable crnum : integer; + begin + crnum := to_integer(unsigned(crnum_in)); + crf_out <= cr_in(crnum * 4 to crnum * 4 + 3); + end process; +end architecture behaviour; diff --git a/testsuite/synth/issue1886/testsuite.sh b/testsuite/synth/issue1886/testsuite.sh new file mode 100755 index 000000000..ddd0fa705 --- /dev/null +++ b/testsuite/synth/issue1886/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 + +for t in test test2; do + synth_tb $t +done + +echo "Test successful" |