testsuite: add a test for #1191

4 files changed, 205 insertions, 0 deletions

diff --git a/testsuite/gna/issue1191/mux_fifo.vhd b/testsuite/gna/issue1191/mux_fifo.vhd
new file mode 100644
index 000000000..e03dff763
--- /dev/null
+++ b/testsuite/gna/issue1191/mux_fifo.vhd
@@ -0,0 +1,99 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.mux_fifo_pkg.all;
+
+entity mux_fifo is
+  generic (g_enabled_channels : std_logic_vector;
+           g_extend           : natural range 0 to 1);
+  port (rst        : in    std_logic;
+        clk        : in    std_logic;
+        -- fifo if
+        fifo_if_in : inout t_mux_fifo_if;
+        -- out if
+        dataout    : out   std_logic_vector;
+        wr_en      : out   std_logic;
+        full       : in    std_logic);
+end entity mux_fifo;
+
+architecture simple of mux_fifo is
+
+  type t_state is (s_wait, s_capture, s_write);
+
+  signal index : integer := -1;
+  signal state : t_state;
+
+  function DetectFirstNonEmpty (EmptyIn : std_logic_vector) return integer is
+  begin
+    for I in EmptyIn'range loop
+      if EmptyIn(I) = '0' then
+        return i;
+      end if;
+    end loop;
+    return -1;
+  end function;
+
+begin
+
+  fifo_if_in.clk <= clk;
+
+  u_mux : process (clk)
+  begin
+
+    if rising_edge(clk) then
+
+      if (rst = '1') then
+
+        index         <= -1;
+        dataout       <= (others => '0');
+        wr_en         <= '0';
+        fifo_if_in.rd <= (others => '0');
+        state         <= s_wait;
+
+      else
+
+        case state is
+
+          when s_wait =>
+
+            -- index   <= DetectFirstNonEmpty(empty and enabled_channels);
+            index         <= DetectFirstNonEmpty(fifo_if_in.empty);
+            dataout       <= (others => '0');
+            wr_en         <= '0';
+            fifo_if_in.rd <= (others => '0');
+            if index >= 0 then
+              fifo_if_in.rd(index) <= '1';
+              state                <= s_capture;
+            end if;
+
+          when s_capture =>
+
+            dataout       <= (others => '0');
+            wr_en         <= '0';
+            fifo_if_in.rd <= (others => '0');
+            if not(full) then
+              state <= s_write;
+            end if;
+
+          when s_write =>
+
+            index <= -1;
+            if g_extend = 1 then
+              dataout <= fifo_if_in.data(index) & std_logic_vector(to_signed(index, 8));
+            else
+              dataout <= fifo_if_in.data(index);
+            end if;
+            wr_en         <= '1';
+            fifo_if_in.rd <= (others => '0');
+            state         <= s_wait;
+
+        end case;
+
+      end if;
+
+    end if;
+
+  end process u_mux;
+
+end architecture simple;
diff --git a/testsuite/gna/issue1191/mux_fifo_pkg.vhd b/testsuite/gna/issue1191/mux_fifo_pkg.vhd
new file mode 100644
index 000000000..b7f94070c
--- /dev/null
+++ b/testsuite/gna/issue1191/mux_fifo_pkg.vhd
@@ -0,0 +1,16 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use ieee.numeric_std.all;
+
+package mux_fifo_pkg is
+
+  type t_mux_fifo_if_data is array (natural range <>) of std_logic_vector;
+
+  type t_mux_fifo_if is record
+    data  : t_mux_fifo_if_data;
+    empty : std_logic_vector;
+    rd    : std_logic_vector;
+    clk   : std_logic;
+  end record t_mux_fifo_if;
+
+end mux_fifo_pkg;
diff --git a/testsuite/gna/issue1191/mux_fifo_tb.vhd b/testsuite/gna/issue1191/mux_fifo_tb.vhd
new file mode 100644
index 000000000..58a60414e
--- /dev/null
+++ b/testsuite/gna/issue1191/mux_fifo_tb.vhd
@@ -0,0 +1,79 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.mux_fifo_pkg.all;
+
+entity mux_fifo_tb is
+  generic (g_nb_channels : natural := 8;
+           g_data_width  : natural := 16);
+  port (rst              : in  std_logic;
+        clk              : in  std_logic;
+        -- fifo in if
+        fifo_in_data     : in  std_logic_vector(g_data_width-1 downto 0);
+        fifo_in_wr       : in  std_logic_vector(g_nb_channels-1 downto 0);
+        fifo_in_full     : out std_logic_vector(g_nb_channels-1 downto 0);
+        -- out if
+        fifo_out_dataout : out std_logic_vector(g_data_width+8-1 downto 0);
+        fifo_out_rd_en   : in  std_logic;
+        fifo_out_empty   : out std_logic);
+end entity mux_fifo_tb;
+
+architecture test_tb of mux_fifo_tb is
+
+  constant ones : std_logic_vector(g_nb_channels-1 downto 0) := (others => '1');
+
+  signal dataout     : std_logic_vector(g_data_width+8-1 downto 0) := (others => '0');
+  signal wr_en, full : std_logic                                   := '0';
+
+  signal fifo_if_in : t_mux_fifo_if(data(g_nb_channels-1 downto 0)(g_data_width-1 downto 0),
+                                    empty(g_nb_channels-1 downto 0),
+                                    rd(g_nb_channels-1 downto 0));
+
+begin
+
+  --u_fifos_in : for i in fifo_in_wr'range generate
+  --  u_fifo_in : entity work.mux_fifo_fifo
+  --    port map (wr_clk => clk,
+  --              wr_rst => rst,
+  --              din    => fifo_in_data,
+  --              wr_en  => fifo_in_wr(i),
+  --              full   => fifo_in_full(i),
+  --              --
+  --              rd_clk => fifo_if_in.clk,
+  --              rd_rst => rst,
+  --              rd_en  => fifo_if_in.rd(i),
+  --              dout   => fifo_if_in.data(i),
+  --              empty  => fifo_if_in.empty(i));
+  --end generate u_fifos_in;
+
+  u_dut : entity work.mux_fifo
+    generic map (g_enabled_channels => ones,
+                 g_extend           => 1)
+    port map (rst        => rst,
+              clk        => clk,
+              -- fifo if
+              fifo_if_in => fifo_if_in,
+              -- out if
+              dataout    => dataout,
+              wr_en      => wr_en,
+              full       => full);
+
+  --u_fifo_out : entity work.mux_fifo_fifo_out
+  --  port map (wr_clk => clk,
+  --            wr_rst => rst,
+  --            din    => dataout,
+  --            wr_en  => wr_en,
+  --            full   => full,
+  --            --
+  --            rd_clk => clk,
+  --            rd_rst => rst,
+  --            rd_en  => fifo_out_rd_en,
+  --            dout   => fifo_out_dataout,
+  --            empty  => fifo_out_empty);
+
+end architecture test_tb;
+
+configuration mux_fifo_tb_test_tb_cfg of mux_fifo_tb is
+  for test_tb
+  end for;
+end mux_fifo_tb_test_tb_cfg;
diff --git a/testsuite/gna/issue1191/testsuite.sh b/testsuite/gna/issue1191/testsuite.sh
new file mode 100755
index 000000000..5d7b3fdd0
--- /dev/null
+++ b/testsuite/gna/issue1191/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS="--std=08 -frelaxed"
+analyze mux_fifo_pkg.vhd mux_fifo.vhd mux_fifo_tb.vhd
+elab_simulate mux_fifo_tb
+
+clean
+
+echo "Test successful"