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| author | Tristan Gingold <tgingold@free.fr> | 2022-07-04 21:12:17 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-07-04 21:12:53 +0200 |
| commit | da2efff4d82663041c133485eac5c1dcd83c3d43 (patch) | |
| tree | 93d5e07b5284d8ab8c0c13a09d7971192a542c7c | |
| parent | c4f2d8305e6798a530f772887dee3592e872ac53 (diff) | |
| download | ghdl-da2efff4d82663041c133485eac5c1dcd83c3d43.tar.gz ghdl-da2efff4d82663041c133485eac5c1dcd83c3d43.tar.bz2 ghdl-da2efff4d82663041c133485eac5c1dcd83c3d43.zip | |
testsuite/synth: add a test for #2123
| -rw-r--r-- | testsuite/synth/issue2123/bug.vhdl | 16 | ||||
| -rwxr-xr-x | testsuite/synth/issue2123/testsuite.sh | 11 |
2 files changed, 27 insertions, 0 deletions
diff --git a/testsuite/synth/issue2123/bug.vhdl b/testsuite/synth/issue2123/bug.vhdl new file mode 100644 index 000000000..d20de9214 --- /dev/null +++ b/testsuite/synth/issue2123/bug.vhdl @@ -0,0 +1,16 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity bug is + port ( + a : in unsigned(8-1 downto 0); + b : in unsigned(8-1 downto 0); + d : out signed(8 downto 0) + ); +end bug; + +architecture behav of bug is +begin + d <= (abs(signed('0' & a) - signed('0' & b))); +end behav; diff --git a/testsuite/synth/issue2123/testsuite.sh b/testsuite/synth/issue2123/testsuite.sh new file mode 100755 index 000000000..502695e50 --- /dev/null +++ b/testsuite/synth/issue2123/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +synth --out=verilog bug.vhdl -e > syn_bug.v + +if grep abs syn_bug.v; then + exit 1 +fi + +echo "Test successful" |