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author | Tristan Gingold <tgingold@free.fr> | 2022-04-15 11:42:06 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-04-15 11:42:06 +0200 |
commit | d71a4391c20867d7e7ccc3a71a90cc4743fef610 (patch) | |
tree | 93623f40aa6d45899e7cd022f2d6cd02236e09d3 | |
parent | a7714952ffaf31d700dc25694fb3f6ebd5ecf320 (diff) | |
download | ghdl-d71a4391c20867d7e7ccc3a71a90cc4743fef610.tar.gz ghdl-d71a4391c20867d7e7ccc3a71a90cc4743fef610.tar.bz2 ghdl-d71a4391c20867d7e7ccc3a71a90cc4743fef610.zip |
testsuite/gna: add a test for previous commit
-rw-r--r-- | testsuite/gna/bug0129/mwe.vhdl | 148 | ||||
-rw-r--r-- | testsuite/gna/bug0129/mwe2.vhdl | 140 | ||||
-rw-r--r-- | testsuite/gna/bug0129/repro1.vhdl | 52 | ||||
-rw-r--r-- | testsuite/gna/bug0129/repro2.vhdl | 51 | ||||
-rwxr-xr-x | testsuite/gna/bug0129/testsuite.sh | 14 |
5 files changed, 405 insertions, 0 deletions
diff --git a/testsuite/gna/bug0129/mwe.vhdl b/testsuite/gna/bug0129/mwe.vhdl new file mode 100644 index 000000000..888634ef1 --- /dev/null +++ b/testsuite/gna/bug0129/mwe.vhdl @@ -0,0 +1,148 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity MWE is + port ( + clk : in std_logic; + start : in std_logic; + continue : in std_logic; + tready : in std_logic + ); +end; + +architecture RTL of MWE is + + constant C_CTR_MAX : natural := 10; + + type t_state is (e_idle, e_count, e_do_something_else); + + type t_rec is record + state : t_state; + ctr : natural range 0 to C_CTR_MAX + 5; + end record t_rec; + + signal r : t_rec := (e_idle, 0); + signal r_next : t_rec; + +begin + + p_main: process (all) + + procedure count ( + constant r_ctr : in natural; + variable v_ctr : out natural + ) is + begin + if r_ctr < C_CTR_MAX then + if tready then + v_ctr := r_ctr + 1; + else + v_ctr := r_ctr; + end if; +-- else <-- missing +-- v_ctr := r_ctr; + end if; + end procedure; + + variable v : t_rec; + + begin + + v := r; + + case r.state is + + when e_idle => + if start then + v.state := e_count; + end if; + + when e_count => + count(r.ctr, v.ctr); + + if continue then + v.ctr := 0; + v.state := e_do_something_else; + end if; + + when e_do_something_else => + v.state := e_idle; + + end case; + + r_next <= v; + + end process p_main; + + p_update_state : process (clk) + begin + if rising_edge(clk) then + assert now /= 105 ns or r_next.ctr = 7 severity failure; + -- report "cntr=" & natural'image(r_next.ctr); + r <= r_next; + end if; + end process; + +end; +library IEEE; +use IEEE.std_logic_1164.all; + +use std.env.stop; + +entity MWE_TB is +end; + +architecture Sim of MWE_TB is + + signal clk : std_logic := '0'; + signal start : std_logic; + signal continue : std_logic; + signal tready : std_logic; + +begin + + clk <= not clk after 5 ns; + + i_DUT : entity work.MWE(RTL) + port map ( + clk => clk, + start => start, + continue => continue, + tready => tready + ); + + p_run : process + + begin + + start <= '0'; + continue <= '0'; + tready <= '0'; + + wait for 15 ns; + + start <= '1'; + + wait for 10 ns; + + start <= '0'; + + wait for 10 ns; + + tready <= '1'; + + wait for 150 ns; + + continue <= '1'; + + wait for 10 ns; + + continue <= '0'; + + wait for 50 ns; + + std.env.stop; + + end process; + +end; diff --git a/testsuite/gna/bug0129/mwe2.vhdl b/testsuite/gna/bug0129/mwe2.vhdl new file mode 100644 index 000000000..6adb64b70 --- /dev/null +++ b/testsuite/gna/bug0129/mwe2.vhdl @@ -0,0 +1,140 @@ +entity MWE is + port ( + clk : in bit; + start : in bit; + continue : in bit; + tready : in bit + ); +end; + +architecture RTL of MWE is + + constant C_CTR_MAX : natural := 10; + + type t_state is (e_idle, e_count, e_do_something_else); + + type t_rec is record + state : t_state; + ctr : natural range 0 to C_CTR_MAX + 5; + end record t_rec; + + signal r : t_rec := (e_idle, 0); + signal r_next : t_rec; + +begin + + p_main: process (all) + + procedure count ( + constant r_ctr : in natural; + variable v_ctr : out natural + ) is + begin + if r_ctr < C_CTR_MAX then + if tready then + v_ctr := r_ctr + 1; + else + v_ctr := r_ctr; + end if; +-- else <-- missing +-- v_ctr := r_ctr; + end if; + end procedure; + + variable v : t_rec; + + begin + + v := r; + + case r.state is + + when e_idle => + if start then + v.state := e_count; + end if; + + when e_count => + count(r.ctr, v.ctr); + + if continue then + v.ctr := 0; + v.state := e_do_something_else; + end if; + + when e_do_something_else => + v.state := e_idle; + + end case; + + r_next <= v; + + end process p_main; + + p_update_state : process (clk) + begin + if rising_edge(clk) then + r <= r_next; + end if; + end process; + +end; +use std.env.stop; + +entity MWE_TB is +end; + +architecture Sim of MWE_TB is + + signal clk : bit := '0'; + signal start : bit; + signal continue : bit; + signal tready : bit; + +begin + + clk <= not clk after 5 ns; + + i_DUT : entity work.MWE(RTL) + port map ( + clk => clk, + start => start, + continue => continue, + tready => tready + ); + + p_run : process + + begin + + start <= '0'; + continue <= '0'; + tready <= '0'; + + wait for 15 ns; + + start <= '1'; + + wait for 10 ns; + + start <= '0'; + + wait for 10 ns; + + tready <= '1'; + + wait for 150 ns; + + continue <= '1'; + + wait for 10 ns; + + continue <= '0'; + + wait for 50 ns; + + std.env.stop; + + end process; + +end; diff --git a/testsuite/gna/bug0129/repro1.vhdl b/testsuite/gna/bug0129/repro1.vhdl new file mode 100644 index 000000000..0f91edfac --- /dev/null +++ b/testsuite/gna/bug0129/repro1.vhdl @@ -0,0 +1,52 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity repro1 is + port (tready : inout std_logic); +end; + +architecture RTL of repro1 is + +-- signal tready : std_logic; + signal cnt : natural; + signal cnt_next : natural; +begin + + p_main: process (all) + + procedure count ( + constant r_ctr : in natural; + variable v_ctr : out natural + ) is + begin + if tready = '1' then + v_ctr := r_ctr + 1; + else + v_ctr := r_ctr; + end if; + end procedure; + + variable v : natural; + + begin + report "execution of process p_main, cnt=" & natural'image(cnt); + count (cnt, v); + + cnt_next <= v; + end process p_main; + + process + begin + tready <= '1'; + cnt <= 1; + wait for 1 ns; + assert cnt_next = 2 severity failure; + cnt <= 2; + wait for 1 ns; + assert cnt_next = 3 severity failure; + tready <= '0'; + wait for 1 ns; + assert cnt_next = 2 severity failure; + wait; + end process; +end; diff --git a/testsuite/gna/bug0129/repro2.vhdl b/testsuite/gna/bug0129/repro2.vhdl new file mode 100644 index 000000000..7f3f5a5e6 --- /dev/null +++ b/testsuite/gna/bug0129/repro2.vhdl @@ -0,0 +1,51 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity repro2 is +end; + +architecture RTL of repro2 is + + signal tready : std_logic; + signal cnt : natural; + signal cnt_next : natural; +begin + + p_main: process (all) + + procedure count ( + constant r_ctr : in natural; + variable v_ctr : out natural + ) is + begin + if tready = '1' then + v_ctr := r_ctr + 1; + else + v_ctr := r_ctr; + end if; + end procedure; + + variable v : natural; + + begin + report "execution of process p_main, cnt=" & natural'image(cnt); + count (cnt, v); + + cnt_next <= v; + end process p_main; + + process + begin + tready <= '1'; + cnt <= 1; + wait for 1 ns; + assert cnt_next = 2 severity failure; + cnt <= 2; + wait for 1 ns; + assert cnt_next = 3 severity failure; + tready <= '0'; + wait for 1 ns; + assert cnt_next = 2 severity failure; + wait; + end process; +end; diff --git a/testsuite/gna/bug0129/testsuite.sh b/testsuite/gna/bug0129/testsuite.sh new file mode 100755 index 000000000..1b2fa83b2 --- /dev/null +++ b/testsuite/gna/bug0129/testsuite.sh @@ -0,0 +1,14 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze mwe.vhdl +elab_simulate mwe + +analyze repro1.vhdl +elab_simulate repro1 + +clean + +echo "Test successful" |