Handle access types.

3 files changed, 64 insertions, 30 deletions

diff --git a/pyGHDL/dom/Literal.py b/pyGHDL/dom/Literal.py
index 10d30b0fa..a2e86b389 100644
--- a/pyGHDL/dom/Literal.py
+++ b/pyGHDL/dom/Literal.py
@@ -52,7 +52,7 @@ __all__ = []
 @export
 class EnumerationLiteral(VHDLModel_EnumerationLiteral):
     @classmethod
-    def parse(cls, literalNode: Iir) -> 'EnumerationLiteral':
+    def parse(cls, literalNode: Iir) -> "EnumerationLiteral":
         literalName = GetNameOfNode(literalNode)
         return cls(literalName)
 
@@ -60,7 +60,7 @@ class EnumerationLiteral(VHDLModel_EnumerationLiteral):
 @export
 class IntegerLiteral(VHDLModel_IntegerLiteral):
     @classmethod
-    def parse(cls, node: Iir) -> 'IntegerLiteral':
+    def parse(cls, node: Iir) -> "IntegerLiteral":
         value = nodes.Get_Value(node)
         return cls(value)
 
@@ -68,7 +68,7 @@ class IntegerLiteral(VHDLModel_IntegerLiteral):
 @export
 class FloatingPointLiteral(VHDLModel_FloatingPointLiteral):
     @classmethod
-    def parse(cls, node: Iir) -> 'FloatingPointLiteral':
+    def parse(cls, node: Iir) -> "FloatingPointLiteral":
         value = nodes.Get_Fp_Value(node)
         return cls(value)
 
@@ -76,7 +76,7 @@ class FloatingPointLiteral(VHDLModel_FloatingPointLiteral):
 @export
 class PhysicalIntegerLiteral(VHDLModel_PhysicalIntegerLiteral):
     @classmethod
-    def parse(cls, node: Iir) -> 'PhysicalIntegerLiteral':
+    def parse(cls, node: Iir) -> "PhysicalIntegerLiteral":
         value = nodes.Get_Value(node)
         unit = nodes.Get_Unit_Name(node)
         unitName = GetNameOfNode(unit)
@@ -87,7 +87,7 @@ class PhysicalIntegerLiteral(VHDLModel_PhysicalIntegerLiteral):
 @export
 class PhysicalFloatingLiteral(VHDLModel_PhysicalFloatingLiteral):
     @classmethod
-    def parse(cls, node: Iir) -> 'PhysicalFloatingLiteral':
+    def parse(cls, node: Iir) -> "PhysicalFloatingLiteral":
         value = nodes.Get_Fp_Value(node)
         unit = nodes.Get_Unit_Name(node)
         unitName = GetNameOfNode(unit)
@@ -98,7 +98,7 @@ class PhysicalFloatingLiteral(VHDLModel_PhysicalFloatingLiteral):
 @export
 class CharacterLiteral(VHDLModel_CharacterLiteral):
     @classmethod
-    def parse(cls, node: Iir) -> 'CharacterLiteral':
+    def parse(cls, node: Iir) -> "CharacterLiteral":
         identifier = nodes.Get_Identifier(node)
         value = name_table.Get_Character(identifier)
         return cls(value)
@@ -107,7 +107,7 @@ class CharacterLiteral(VHDLModel_CharacterLiteral):
 @export
 class StringLiteral(VHDLModel_StringLiteral):
     @classmethod
-    def parse(cls, node: Iir) -> 'StringLiteral':
+    def parse(cls, node: Iir) -> "StringLiteral":
         stringID = nodes.Get_String8_Id(node)
         value = name_table.Get_Name_Ptr(stringID)
         return cls(value)
diff --git a/pyGHDL/dom/Type.py b/pyGHDL/dom/Type.py
index 38cd8f5a4..3f43188a6 100644
--- a/pyGHDL/dom/Type.py
+++ b/pyGHDL/dom/Type.py
@@ -49,7 +49,6 @@ from pyVHDLModel.VHDLModel import (
     RecordType as VHDLModel_RecordType,
     AccessType as VHDLModel_AccessType,
     SubType as VHDLModel_SubType,
-    Expression,
 )
 
 
@@ -64,7 +63,7 @@ class IntegerType(VHDLModel_IntegerType):
 @export
 class EnumeratedType(VHDLModel_EnumeratedType):
     @classmethod
-    def parse(cls, typeName: str, typeDefinitionNode: Iir):
+    def parse(cls, typeName: str, typeDefinitionNode: Iir) -> "EnumeratedType":
         literals = []
         enumerationLiterals = nodes.Get_Enumeration_Literal_List(typeDefinitionNode)
         for enumerationLiteral in utils.flist_iter(enumerationLiterals):
@@ -77,8 +76,11 @@ class EnumeratedType(VHDLModel_EnumeratedType):
 @export
 class ArrayType(VHDLModel_ArrayType):
     @classmethod
-    def parse(cls, typeName: str, typeDefinitionNode: Iir):
-        from pyGHDL.dom._Translate import GetSimpleTypeFromNode, GetSubTypeIndicationFromNode
+    def parse(cls, typeName: str, typeDefinitionNode: Iir) -> "ArrayType":
+        from pyGHDL.dom._Translate import (
+            GetSimpleTypeFromNode,
+            GetSubTypeIndicationFromNode,
+        )
 
         indices = []
         indexDefinitions = nodes.Get_Index_Subtype_Definition_List(typeDefinitionNode)
@@ -94,30 +96,38 @@ class ArrayType(VHDLModel_ArrayType):
                     )
                 )
 
-        elementSubTypeIndication = nodes.Get_Element_Subtype_Indication(typeDefinitionNode)
-        elementSubType = GetSubTypeIndicationFromNode(elementSubTypeIndication, "array declaration", typeName)
+        elementSubTypeIndication = nodes.Get_Element_Subtype_Indication(
+            typeDefinitionNode
+        )
+        elementSubType = GetSubTypeIndicationFromNode(
+            elementSubTypeIndication, "array declaration", typeName
+        )
 
         return cls(typeName, indices, elementSubType)
 
 
 @export
 class RecordTypeElement(VHDLModel_RecordTypeElement):
-    pass
+    @classmethod
+    def parse(cls, elementDeclarationNode: Iir) -> "RecordTypeElement":
+        from pyGHDL.dom._Translate import GetSubtypeIndicationFromNode
+
+        elementName = GetNameOfNode(elementDeclarationNode)
+        elementType = GetSubtypeIndicationFromNode(
+            elementDeclarationNode, "record element", elementName
+        )
+
+        return cls(elementName, elementType)
 
 
 @export
 class RecordType(VHDLModel_RecordType):
     @classmethod
-    def parse(cls, typeName: str, typeDefinitionNode: Iir):
-        from pyGHDL.dom._Translate import GetSubtypeIndicationFromNode
-
+    def parse(cls, typeName: str, typeDefinitionNode: Iir) -> "RecordType":
         elements = []
         elementDeclarations = nodes.Get_Elements_Declaration_List(typeDefinitionNode)
         for elementDeclaration in utils.flist_iter(elementDeclarations):
-            elementName = GetNameOfNode(elementDeclaration)
-            elementType = GetSubtypeIndicationFromNode(elementDeclaration, "record element", elementName)
-
-            element = RecordTypeElement(elementName, elementType)
+            element = RecordTypeElement.parse(elementDeclaration)
             elements.append(element)
 
         return cls(typeName, elements)
@@ -125,7 +135,18 @@ class RecordType(VHDLModel_RecordType):
 
 @export
 class AccessType(VHDLModel_AccessType):
-    pass
+    @classmethod
+    def parse(cls, typeName: str, typeDefinitionNode: Iir) -> "AccessType":
+        from pyGHDL.dom._Translate import GetSubtypeIndicationFromNode
+
+        designatedSubtypeIndication = nodes.Get_Designated_Subtype_Indication(
+            typeDefinitionNode
+        )
+        designatedSubType = GetSubtypeIndicationFromNode(
+            designatedSubtypeIndication, "access type", typeName, do=False
+        )
+
+        return cls(typeName, designatedSubType)
 
 
 @export
diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py
index 8cb1639fd..8627fd5cb 100644
--- a/pyGHDL/dom/_Translate.py
+++ b/pyGHDL/dom/_Translate.py
@@ -73,7 +73,8 @@ from pyGHDL.dom.Literal import (
     FloatingPointLiteral,
     StringLiteral,
     PhysicalIntegerLiteral,
-    PhysicalFloatingLiteral, EnumerationLiteral,
+    PhysicalFloatingLiteral,
+    EnumerationLiteral,
 )
 from pyGHDL.dom.Expression import (
     SubtractionExpression,
@@ -116,8 +117,13 @@ __all__ = []
 
 
 @export
-def GetSubtypeIndicationFromNode(node: Iir, entity: str, name: str) -> SubTypeOrSymbol:
-    subTypeIndication = nodes.Get_Subtype_Indication(node)
+def GetSubtypeIndicationFromNode(
+    node: Iir, entity: str, name: str, do=True
+) -> SubTypeOrSymbol:
+    if do:
+        subTypeIndication = nodes.Get_Subtype_Indication(node)
+    else:
+        subTypeIndication = node
     if subTypeIndication is nodes.Null_Iir:
         return None
     subTypeKind = GetIirKindOfNode(subTypeIndication)
@@ -190,6 +196,7 @@ def GetArrayConstraintsFromSubtypeIndication(
 def GetTypeFromNode(node: Iir) -> BaseType:
     typeName = GetNameOfNode(node)
     typeDefinition = nodes.Get_Type_Definition(node)
+
     kind = GetIirKindOfNode(typeDefinition)
     if kind == nodes.Iir_Kind.Range_Expression:
         r = GetRangeFromNode(typeDefinition)
@@ -206,9 +213,7 @@ def GetTypeFromNode(node: Iir) -> BaseType:
     elif kind == nodes.Iir_Kind.Record_Type_Definition:
         return RecordType.parse(typeName, typeDefinition)
     elif kind == nodes.Iir_Kind.Access_Type_Definition:
-        designatedType = nodes.Get_Designated_Type(typeDefinition)
-
-        return AccessType(typeName, designatedType)
+        return AccessType.parse(typeName, typeDefinition)
     else:
         position = GetPositionOfNode(typeDefinition)
         raise DOMException(
@@ -224,7 +229,9 @@ def GetTypeFromNode(node: Iir) -> BaseType:
 
 
 @export
-def GetSubTypeIndicationFromNode(subTypeIndicationNode: Iir, entity: str, name: str) -> SubTypeOrSymbol:
+def GetSubTypeIndicationFromNode(
+    subTypeIndicationNode: Iir, entity: str, name: str
+) -> SubTypeOrSymbol:
     kind = GetIirKindOfNode(subTypeIndicationNode)
     if kind == nodes.Iir_Kind.Simple_Name:
         return GetSimpleTypeFromNode(subTypeIndicationNode)
@@ -237,25 +244,31 @@ def GetSubTypeIndicationFromNode(subTypeIndicationNode: Iir, entity: str, name:
             )
         )
 
+
 @export
 def GetSimpleTypeFromNode(subTypeIndicationNode: Iir) -> SimpleSubTypeSymbol:
     subTypeName = GetNameOfNode(subTypeIndicationNode)
     return SimpleSubTypeSymbol(subTypeName)
 
+
 @export
-def GetConstrainedSubTypeFromNode(subTypeIndicationNode: Iir) -> ConstrainedSubTypeSymbol:
+def GetConstrainedSubTypeFromNode(
+    subTypeIndicationNode: Iir,
+) -> ConstrainedSubTypeSymbol:
     typeMark = nodes.Get_Subtype_Type_Mark(subTypeIndicationNode)
     typeMarkName = GetNameOfNode(typeMark)
 
     constraints = GetArrayConstraintsFromSubtypeIndication(subTypeIndicationNode)
     return ConstrainedSubTypeSymbol(typeMarkName, constraints)
 
+
 @export
 def GetSubTypeFromNode(node: Iir) -> SubTypeOrSymbol:
     subTypeName = GetNameOfNode(node)
 
     return SubType(subTypeName)
 
+
 @export
 def GetRangeFromNode(node: Iir) -> Range:
     direction = nodes.Get_Direction(node)