testsuite/gna: add a test and close #1224

3 files changed, 59 insertions, 0 deletions

diff --git a/testsuite/gna/issue1224/tb.vhdl b/testsuite/gna/issue1224/tb.vhdl
new file mode 100644
index 000000000..861c445cd
--- /dev/null
+++ b/testsuite/gna/issue1224/tb.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity tb is
+end;
+
+architecture arch of tb is
+
+  type ulogic_mat_t is array(natural range <>) of std_logic_vector; --this requires vhdl08
+
+begin
+  process
+    constant logic2D: ulogic_mat_t(0 to 1) := (('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'), ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'));
+  begin
+
+    for i in logic2D'range loop
+      for j in logic2D'range(1) loop
+        report "2D [" & integer'image(i) & "," & integer'image(j) & "]: " & std_logic'image(logic2D(i)(j)) severity note;
+      end loop ;
+    end loop ;
+
+    wait;
+  end process;
+end;
diff --git a/testsuite/gna/issue1224/tb93.vhdl b/testsuite/gna/issue1224/tb93.vhdl
new file mode 100644
index 000000000..c1c9bc4e8
--- /dev/null
+++ b/testsuite/gna/issue1224/tb93.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity tb is
+end;
+
+architecture arch of tb is
+
+  type ulogic_mat_t is array(natural range <>, natural range <>) of std_logic; --this requires vhdl08
+
+begin
+  process
+    constant logic2D: ulogic_mat_t(0 to 1, 0 to 8) := (('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'), ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'));
+  begin
+
+    for i in logic2D'range loop
+      for j in logic2D'range(2) loop
+        report "2D [" & integer'image(i) & "," & integer'image(j) & "]: " & std_logic'image(logic2D(i,j)) severity note;
+      end loop ;
+    end loop ;
+
+    wait;
+  end process;
+end;
diff --git a/testsuite/gna/issue1224/testsuite.sh b/testsuite/gna/issue1224/testsuite.sh
new file mode 100755
index 000000000..de8596797
--- /dev/null
+++ b/testsuite/gna/issue1224/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze tb.vhdl
+elab_simulate tb
+
+clean
+
+echo "Test successful"