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author | Tristan Gingold <tgingold@free.fr> | 2019-12-01 08:57:39 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-12-01 19:42:07 +0100 |
commit | d11ad2282157564dad9e53eccf9f2ec8a05bbda7 (patch) | |
tree | c7ad54a58650f92d0e864949c6781ad66749a982 | |
parent | 54f71559b50c01fc08b6c07b7d92635de81f8905 (diff) | |
download | ghdl-d11ad2282157564dad9e53eccf9f2ec8a05bbda7.tar.gz ghdl-d11ad2282157564dad9e53eccf9f2ec8a05bbda7.tar.bz2 ghdl-d11ad2282157564dad9e53eccf9f2ec8a05bbda7.zip |
testcase: complete test for #1044.
-rw-r--r-- | testsuite/synth/issue1044/ent.vhdl | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/testsuite/synth/issue1044/ent.vhdl b/testsuite/synth/issue1044/ent.vhdl index fc98054d0..5c0fb6471 100644 --- a/testsuite/synth/issue1044/ent.vhdl +++ b/testsuite/synth/issue1044/ent.vhdl @@ -13,6 +13,9 @@ end; architecture a of ent is constant fmul : real := val * 5.0; constant fneg : real := -val; + constant fid : real := +val; + constant fabs : real := abs val; + constant fexp : real := val ** 2; begin lt <= '1' when VAL < 1.5 else '0'; end; |