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| author | Tristan Gingold <tgingold@free.fr> | 2020-04-20 07:49:03 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-04-20 12:19:48 +0200 |
| commit | cb72a1834f160d95d026b7e466886fd95fd82146 (patch) | |
| tree | 87cd0fff5a8ce03b05b8e6a0a0129b60de90fe61 | |
| parent | b6d42a577f4ee5f2084a165b0cdf66cadcc878a1 (diff) | |
| download | ghdl-cb72a1834f160d95d026b7e466886fd95fd82146.tar.gz ghdl-cb72a1834f160d95d026b7e466886fd95fd82146.tar.bz2 ghdl-cb72a1834f160d95d026b7e466886fd95fd82146.zip | |
types: introduce Direction_Type, which replaces Iir_Direction.
Global renaming.
44 files changed, 293 insertions, 302 deletions
diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index 4f93775a0..1df7f9445 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -962,11 +962,6 @@ class Iir_Constraint: Fully_Constrained = 2 -class Iir_Direction: - To = 0 - Downto = 1 - - class Iir_Delay_Mechanism: Inertial_Delay = 0 Transport_Delay = 1 diff --git a/python/libghdl/thin/vhdl/nodes_meta.py b/python/libghdl/thin/vhdl/nodes_meta.py index e8091798d..e2a9d7eb0 100644 --- a/python/libghdl/thin/vhdl/nodes_meta.py +++ b/python/libghdl/thin/vhdl/nodes_meta.py @@ -18,13 +18,13 @@ class types: Boolean = 0 Date_State_Type = 1 Date_Type = 2 - File_Checksum_Id = 3 - Fp64 = 4 - Iir = 5 - Iir_All_Sensitized = 6 - Iir_Constraint = 7 - Iir_Delay_Mechanism = 8 - Iir_Direction = 9 + Direction_Type = 3 + File_Checksum_Id = 4 + Fp64 = 5 + Iir = 6 + Iir_All_Sensitized = 7 + Iir_Constraint = 8 + Iir_Delay_Mechanism = 9 Iir_Flist = 10 Iir_Index32 = 11 Iir_Int32 = 12 @@ -430,6 +430,8 @@ Get_Date_State_Type = libghdl.vhdl__nodes_meta__get_date_state_type Get_Date_Type = libghdl.vhdl__nodes_meta__get_date_type +Get_Direction_Type = libghdl.vhdl__nodes_meta__get_direction_type + Get_File_Checksum_Id = libghdl.vhdl__nodes_meta__get_file_checksum_id Get_Fp64 = libghdl.vhdl__nodes_meta__get_fp64 @@ -442,8 +444,6 @@ Get_Iir_Constraint = libghdl.vhdl__nodes_meta__get_iir_constraint Get_Iir_Delay_Mechanism = libghdl.vhdl__nodes_meta__get_iir_delay_mechanism -Get_Iir_Direction = libghdl.vhdl__nodes_meta__get_iir_direction - Get_Iir_Flist = libghdl.vhdl__nodes_meta__get_iir_flist Get_Iir_Index32 = libghdl.vhdl__nodes_meta__get_iir_index32 diff --git a/python/xtools/pnodespy.py b/python/xtools/pnodespy.py index 641452def..fb3ec7114 100755 --- a/python/xtools/pnodespy.py +++ b/python/xtools/pnodespy.py @@ -147,7 +147,6 @@ Iir_Flist_All = 2 read_spec_enum('Iir_Mode', 'Iir_', 'Iir_Mode') read_spec_enum('Iir_Staticness', '', 'Iir_Staticness') read_spec_enum('Iir_Constraint', '', 'Iir_Constraint') - read_spec_enum('Iir_Direction', 'Iir_', 'Iir_Direction') read_spec_enum('Iir_Delay_Mechanism', 'Iir_', 'Iir_Delay_Mechanism') read_spec_enum('Date_State_Type', 'Date_', 'Date_State') read_spec_enum('Iir_Predefined_Functions', diff --git a/src/ghdldrv/ghdlxml.adb b/src/ghdldrv/ghdlxml.adb index 3829dc0a8..46bffd9ea 100644 --- a/src/ghdldrv/ghdlxml.adb +++ b/src/ghdldrv/ghdlxml.adb @@ -394,9 +394,9 @@ package body Ghdlxml is when Type_Iir_Predefined_Functions => Put_Field (F, Image_Iir_Predefined_Functions (Get_Iir_Predefined_Functions (N, F))); - when Type_Iir_Direction => - Put_Field (F, Image_Iir_Direction - (Get_Iir_Direction (N, F))); + when Type_Direction_Type => + Put_Field (F, Image_Direction_Type + (Get_Direction_Type (N, F))); when Type_Iir_Int32 => Put_Field (F, Strip (Iir_Int32'Image (Get_Iir_Int32 (N, F)))); diff --git a/src/synth/synth-aggr.adb b/src/synth/synth-aggr.adb index b0f627bd2..ad8b5ea05 100644 --- a/src/synth/synth-aggr.adb +++ b/src/synth/synth-aggr.adb @@ -43,14 +43,14 @@ package body Synth.Aggr is Right : constant Int64 := Int64 (Bounds.Right); begin case Bounds.Dir is - when Iir_To => + when Dir_To => if Index >= Left and then Index <= Right then -- to Off := Uns32 (Index - Left); Err_P := False; return; end if; - when Iir_Downto => + when Dir_Downto => if Index <= Left and then Index >= Right then -- downto Off := Uns32 (Left - Index); diff --git a/src/synth/synth-decls.adb b/src/synth/synth-decls.adb index 003505bc6..81d8a20c9 100644 --- a/src/synth/synth-decls.adb +++ b/src/synth/synth-decls.adb @@ -199,7 +199,7 @@ package body Synth.Decls is W : Width; begin W := Uns32 (Clog2 (Uns64 (Nbr_El))); - Rng := (Dir => Iir_To, + Rng := (Dir => Dir_To, Is_Signed => False, Left => 0, Right => Int64 (Nbr_El - 1)); diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb index 6736343ff..885077e6f 100644 --- a/src/synth/synth-disp_vhdl.adb +++ b/src/synth/synth-disp_vhdl.adb @@ -187,9 +187,9 @@ package body Synth.Disp_Vhdl is begin for I in 0 .. Bnd.Len - 1 loop case Bnd.Dir is - when Iir_To => + when Dir_To => Idx := Bnd.Left + Int32 (I); - when Iir_Downto => + when Dir_Downto => Idx := Bnd.Left - Int32 (I); end case; Disp_In_Converter @@ -343,9 +343,9 @@ package body Synth.Disp_Vhdl is begin for I in 0 .. Bnd.Len - 1 loop case Bnd.Dir is - when Iir_To => + when Dir_To => Idx := Bnd.Left + Int32 (I); - when Iir_Downto => + when Dir_Downto => Idx := Bnd.Left - Int32 (I); end case; Disp_Out_Converter diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index 54f8d9916..87f3c4ac1 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -418,7 +418,7 @@ package body Synth.Expr is end Concat_Array; function Synth_Discrete_Range_Expression - (L : Int64; R : Int64; Dir : Iir_Direction) return Discrete_Range_Type is + (L : Int64; R : Int64; Dir : Direction_Type) return Discrete_Range_Type is begin return (Dir => Dir, Left => L, @@ -585,10 +585,10 @@ package body Synth.Expr is B := Synth_Array_Attribute (Syn_Inst, Bound); -- Reverse case B.Dir is - when Iir_To => - B.Dir := Iir_Downto; - when Iir_Downto => - B.Dir := Iir_To; + when Dir_To => + B.Dir := Dir_Downto; + when Dir_Downto => + B.Dir := Dir_To; end case; T := B.Right; B.Right := B.Left; @@ -924,7 +924,7 @@ package body Synth.Expr is Res : Valtyp; begin Bnd := Create_Bound_Array (1); - Bnd.D (1) := (Dir => Iir_To, Left => 1, Right => Int32 (Len), + Bnd.D (1) := (Dir => Dir_To, Left => 1, Right => Int32 (Len), Len => Width (Len)); Typ := Create_Array_Type (Bnd, Styp.Uarr_El); @@ -1011,9 +1011,9 @@ package body Synth.Expr is function In_Bounds (Bnd : Bound_Type; V : Int32) return Boolean is begin case Bnd.Dir is - when Iir_To => + when Dir_To => return V >= Bnd.Left and then V <= Bnd.Right; - when Iir_Downto => + when Dir_Downto => return V <= Bnd.Left and then V >= Bnd.Right; end case; end In_Bounds; @@ -1034,10 +1034,10 @@ package body Synth.Expr is -- The offset is from the LSB (bit 0). Bit 0 is the rightmost one. case Bnd.Dir is - when Iir_To => + when Dir_To => Res.Net_Off := Uns32 (Bnd.Right - Int32 (Idx)); Res.Mem_Off := Size_Type (Int32 (Idx) - Bnd.Left); - when Iir_Downto => + when Dir_Downto => Res.Net_Off := Uns32 (Int32 (Idx) - Bnd.Right); Res.Mem_Off := Size_Type (Bnd.Left - Int32 (Idx)); end case; @@ -1056,7 +1056,7 @@ package body Synth.Expr is Wbounds := Clog2 (Bnd.Len); Idx2 := Synth_Resize (Idx_Val, Wbounds, Loc); - if Bnd.Right = 0 and then Bnd.Dir = Iir_Downto then + if Bnd.Right = 0 and then Bnd.Dir = Dir_Downto then -- Simple case without adjustments. return Idx2; end if; @@ -1066,10 +1066,10 @@ package body Synth.Expr is Set_Location (Right, Loc); case Bnd.Dir is - when Iir_To => + when Dir_To => -- L <= I <= R --> off = R - I Off := Build_Dyadic (Build_Context, Id_Sub, Right, Idx2); - when Iir_Downto => + when Dir_Downto => -- L >= I >= R --> off = I - R Off := Build_Dyadic (Build_Context, Id_Sub, Idx2, Right); end case; @@ -1321,10 +1321,10 @@ package body Synth.Expr is end if; case Pfx_Bnd.Dir is - when Iir_To => + when Dir_To => Off := Uns32 (L_Add - Pfx_Bnd.Left); Width := Uns32 (R_Add - L_Add + 1); - when Iir_Downto => + when Dir_Downto => Off := Uns32 (R_Add - Pfx_Bnd.Right); Width := Uns32 (L_Add - R_Add + 1); end case; @@ -1335,7 +1335,7 @@ package body Synth.Expr is Name : Node; Pfx_Bnd : Bound_Type; L, R : Int64; - Dir : Iir_Direction; + Dir : Direction_Type; El_Typ : Type_Acc; Res_Bnd : out Bound_Type; Off : out Value_Offsets) @@ -1346,19 +1346,19 @@ package body Synth.Expr is if Pfx_Bnd.Dir /= Dir then Error_Msg_Synth (+Name, "direction mismatch in slice"); Off := (0, 0); - if Dir = Iir_To then - Res_Bnd := (Dir => Iir_To, Left => 1, Right => 0, Len => 0); + if Dir = Dir_To then + Res_Bnd := (Dir => Dir_To, Left => 1, Right => 0, Len => 0); else - Res_Bnd := (Dir => Iir_Downto, Left => 0, Right => 1, Len => 0); + Res_Bnd := (Dir => Dir_Downto, Left => 0, Right => 1, Len => 0); end if; return; end if; -- Might be a null slice. case Pfx_Bnd.Dir is - when Iir_To => + when Dir_To => Is_Null := L > R; - when Iir_Downto => + when Dir_Downto => Is_Null := L < R; end case; if Is_Null then @@ -1375,11 +1375,11 @@ package body Synth.Expr is end if; case Pfx_Bnd.Dir is - when Iir_To => + when Dir_To => Len := Uns32 (R - L + 1); Off.Net_Off := Uns32 (Pfx_Bnd.Right - Int32 (R)) * El_Typ.W; Off.Mem_Off := Size_Type (Int32 (L) - Pfx_Bnd.Left) * El_Typ.Sz; - when Iir_Downto => + when Dir_Downto => Len := Uns32 (L - R + 1); Off.Net_Off := Uns32 (Int32 (R) - Pfx_Bnd.Right) * El_Typ.W; Off.Mem_Off := Size_Type (Pfx_Bnd.Left - Int32 (L)) * El_Typ.Sz; @@ -1401,7 +1401,7 @@ package body Synth.Expr is is Expr : constant Node := Get_Suffix (Name); Left, Right : Valtyp; - Dir : Iir_Direction; + Dir : Direction_Type; Step : Uns32; Max : Uns32; Inp_W : Width; @@ -1445,10 +1445,10 @@ package body Synth.Expr is Error_Msg_Synth (+Name, "direction mismatch in slice"); Inp := No_Net; Off := (0, 0); - if Dir = Iir_To then - Res_Bnd := (Dir => Iir_To, Left => 1, Right => 0, Len => 0); + if Dir = Dir_To then + Res_Bnd := (Dir => Dir_To, Left => 1, Right => 0, Len => 0); else - Res_Bnd := (Dir => Iir_Downto, Left => 0, Right => 1, Len => 0); + Res_Bnd := (Dir => Dir_Downto, Left => 0, Right => 1, Len => 0); end if; return; end if; @@ -1705,7 +1705,7 @@ package body Synth.Expr is -- Return the left bound if the direction of the range is LEFT_DIR. function Synth_Low_High_Type_Attribute - (Syn_Inst : Synth_Instance_Acc; Expr : Node; Left_Dir : Iir_Direction) + (Syn_Inst : Synth_Instance_Acc; Expr : Node; Left_Dir : Direction_Type) return Valtyp is Typ : Type_Acc; @@ -1965,9 +1965,9 @@ package body Synth.Expr is begin B := Synth_Array_Attribute (Syn_Inst, Expr); case B.Dir is - when Iir_To => + when Dir_To => V := B.Right; - when Iir_Downto => + when Dir_Downto => V := B.Left; end case; return Create_Value_Discrete (Int64 (V), Expr_Type); @@ -1979,9 +1979,9 @@ package body Synth.Expr is begin B := Synth_Array_Attribute (Syn_Inst, Expr); case B.Dir is - when Iir_To => + when Dir_To => V := B.Left; - when Iir_Downto => + when Dir_Downto => V := B.Right; end case; return Create_Value_Discrete (Int64 (V), Expr_Type); @@ -2007,9 +2007,9 @@ package body Synth.Expr is return Synth_Subtype_Conversion (V, Dtype, False, Expr); end; when Iir_Kind_Low_Type_Attribute => - return Synth_Low_High_Type_Attribute (Syn_Inst, Expr, Iir_To); + return Synth_Low_High_Type_Attribute (Syn_Inst, Expr, Dir_To); when Iir_Kind_High_Type_Attribute => - return Synth_Low_High_Type_Attribute (Syn_Inst, Expr, Iir_Downto); + return Synth_Low_High_Type_Attribute (Syn_Inst, Expr, Dir_Downto); when Iir_Kind_Value_Attribute => return Synth_Value_Attribute (Syn_Inst, Expr); when Iir_Kind_Image_Attribute => diff --git a/src/synth/synth-expr.ads b/src/synth/synth-expr.ads index d03f2f92c..ef0499dc1 100644 --- a/src/synth/synth-expr.ads +++ b/src/synth/synth-expr.ads @@ -90,7 +90,7 @@ package Synth.Expr is Dim : Dim_Type) return Bound_Type; function Synth_Discrete_Range_Expression - (L : Int64; R : Int64; Dir : Iir_Direction) return Discrete_Range_Type; + (L : Int64; R : Int64; Dir : Direction_Type) return Discrete_Range_Type; function Synth_Discrete_Range_Expression (Syn_Inst : Synth_Instance_Acc; Rng : Node) return Discrete_Range_Type; function Synth_Float_Range_Expression diff --git a/src/synth/synth-insts.adb b/src/synth/synth-insts.adb index e4c5cf608..bdc9f040a 100644 --- a/src/synth/synth-insts.adb +++ b/src/synth/synth-insts.adb @@ -171,7 +171,7 @@ package body Synth.Insts is procedure Hash_Bound (C : in out GNAT.SHA1.Context; B : Bound_Type) is begin - Hash_Uns64 (C, Iir_Direction'Pos (B.Dir)); + Hash_Uns64 (C, Direction_Type'Pos (B.Dir)); Hash_Uns64 (C, To_Uns64 (Int64 (B.Left))); Hash_Uns64 (C, To_Uns64 (Int64 (B.Right))); end Hash_Bound; diff --git a/src/synth/synth-objtypes.adb b/src/synth/synth-objtypes.adb index cd199d724..8c9867a28 100644 --- a/src/synth/synth-objtypes.adb +++ b/src/synth/synth-objtypes.adb @@ -124,10 +124,10 @@ package body Synth.Objtypes is W : Width; begin case Rng.Dir is - when Iir_To => + when Dir_To => Lo := Rng.Left; Hi := Rng.Right; - when Iir_Downto => + when Dir_Downto => Lo := Rng.Right; Hi := Rng.Left; end case; @@ -250,7 +250,7 @@ package body Synth.Objtypes is function Create_Vec_Type_By_Length (Len : Width; El : Type_Acc) return Type_Acc is begin - return Create_Vector_Type ((Dir => Iir_Downto, + return Create_Vector_Type ((Dir => Dir_Downto, Left => Int32 (Len) - 1, Right => 0, Len => Len), @@ -370,9 +370,9 @@ package body Synth.Objtypes is Len : Int64; begin case Rng.Dir is - when Iir_To => + when Dir_To => Len := Rng.Right - Rng.Left + 1; - when Iir_Downto => + when Dir_Downto => Len := Rng.Left - Rng.Right + 1; end case; if Len < 0 then diff --git a/src/synth/synth-objtypes.ads b/src/synth/synth-objtypes.ads index a332536d1..c79a473c4 100644 --- a/src/synth/synth-objtypes.ads +++ b/src/synth/synth-objtypes.ads @@ -30,7 +30,7 @@ with Vhdl.Nodes; use Vhdl.Nodes; package Synth.Objtypes is type Discrete_Range_Type is record -- An integer range. - Dir : Iir_Direction; + Dir : Direction_Type; -- Netlist representation: signed or unsigned, width of vector. Is_Signed : Boolean; @@ -43,13 +43,13 @@ package Synth.Objtypes is function Discrete_Range_Width (Rng : Discrete_Range_Type) return Width; type Float_Range_Type is record - Dir : Iir_Direction; + Dir : Direction_Type; Left : Fp64; Right : Fp64; end record; type Bound_Type is record - Dir : Iir_Direction; + Dir : Direction_Type; Left : Int32; Right : Int32; Len : Width; diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index 758ca6b06..2ee88c328 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -128,7 +128,7 @@ package body Synth.Oper is begin Res := Prev.Typ; - if Res.Vbound.Dir = Iir_Downto + if Res.Vbound.Dir = Dir_Downto and then Res.Vbound.Right = 0 then -- Normalized range @@ -156,16 +156,16 @@ package body Synth.Oper is -- Special case. Res.Right := Res.Left; case Index_Bounds.Dir is - when Iir_To => + when Dir_To => Res.Left := Res.Right + 1; - when Iir_Downto => + when Dir_Downto => Res.Left := Res.Right - 1; end case; else case Index_Bounds.Dir is - when Iir_To => + when Dir_To => Res.Right := Res.Left + Int32 (Len - 1); - when Iir_Downto => + when Dir_Downto => Res.Right := Res.Left - Int32 (Len - 1); end case; end if; diff --git a/src/synth/synth-static_oper.adb b/src/synth/synth-static_oper.adb index 64316280d..e4249740f 100644 --- a/src/synth/synth-static_oper.adb +++ b/src/synth/synth-static_oper.adb @@ -226,7 +226,7 @@ package body Synth.Static_Oper is function Create_Res_Bound (Prev : Type_Acc) return Type_Acc is begin - if Prev.Vbound.Dir = Iir_Downto + if Prev.Vbound.Dir = Dir_Downto and then Prev.Vbound.Right = 0 then -- Normalized range diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb index b41a9ba69..efece924c 100644 --- a/src/synth/synth-stmts.adb +++ b/src/synth/synth-stmts.adb @@ -1119,9 +1119,9 @@ package body Synth.Stmts is Synth_Discrete_Range (C.Inst, Get_Choice_Range (Choice), Bnd); case Bnd.Dir is - when Iir_To => + when Dir_To => Is_In := Sel >= Bnd.Left and Sel <= Bnd.Right; - when Iir_Downto => + when Dir_Downto => Is_In := Sel <= Bnd.Left and Sel >= Bnd.Right; end case; if Is_In then @@ -1970,9 +1970,9 @@ package body Synth.Stmts is function In_Range (Rng : Discrete_Range_Type; V : Int64) return Boolean is begin case Rng.Dir is - when Iir_To => + when Dir_To => return V >= Rng.Left and then V <= Rng.Right; - when Iir_Downto => + when Dir_Downto => return V <= Rng.Left and then V >= Rng.Right; end case; end In_Range; @@ -1983,9 +1983,9 @@ package body Synth.Stmts is begin T := Read_Discrete (V); case Rng.Dir is - when Iir_To => + when Dir_To => T := T + 1; - when Iir_Downto => + when Dir_Downto => T := T - 1; end case; Write_Discrete (V, T); diff --git a/src/synth/synth-values-debug.adb b/src/synth/synth-values-debug.adb index e28b3ab5e..493c30e7e 100644 --- a/src/synth/synth-values-debug.adb +++ b/src/synth/synth-values-debug.adb @@ -23,12 +23,12 @@ with Utils_IO; use Utils_IO; with Vhdl.Nodes; use Vhdl.Nodes; package body Synth.Values.Debug is - procedure Put_Dir (Dir : Iir_Direction) is + procedure Put_Dir (Dir : Direction_Type) is begin case Dir is - when Iir_To => + when Dir_To => Put ("to"); - when Iir_Downto => + when Dir_Downto => Put ("downto"); end case; end Put_Dir; diff --git a/src/types.ads b/src/types.ads index e118a108c..2b6fa412c 100644 --- a/src/types.ads +++ b/src/types.ads @@ -181,6 +181,9 @@ package Types is -- Result of a comparaison of two numeric values. type Order_Type is (Less, Equal, Greater); + -- Direction for a range. Used by many HDLs! + type Direction_Type is (Dir_To, Dir_Downto); + -- Modular type for the size. We don't use Storage_Offset in order to -- make alignment computation efficient (knowing that alignment is a -- power of two). diff --git a/src/vhdl/simulate/simul-environments.adb b/src/vhdl/simulate/simul-environments.adb index 356383bba..221e812d7 100644 --- a/src/vhdl/simulate/simul-environments.adb +++ b/src/vhdl/simulate/simul-environments.adb @@ -19,7 +19,7 @@ with System; with Ada.Unchecked_Conversion; with GNAT.Debug_Utilities; -with Types; use Types; + with Simple_IO; with Name_Table; with Simul.Debugger; use Simul.Debugger; @@ -207,9 +207,9 @@ package body Simul.Environments is begin Cmp := Compare_Value (Arange.Left, Arange.Right); case Arange.Dir is - when Iir_To => + when Dir_To => return Cmp = Greater; - when Iir_Downto => + when Dir_Downto => return Cmp = Less; end case; end Is_Null_Range; @@ -462,22 +462,20 @@ package body Simul.Environments is (Kind => Iir_Value_Access, Val_Access => Val))); end Create_Access_Value; - function Create_Range_Value - (Left, Right : Iir_Value_Literal_Acc; - Dir : Iir_Direction; - Length : Iir_Index32) - return Iir_Value_Literal_Acc + function Create_Range_Value (Left, Right : Iir_Value_Literal_Acc; + Dir : Direction_Type; + Length : Iir_Index32) + return Iir_Value_Literal_Acc is subtype Range_Value is Iir_Value_Literal (Iir_Value_Range); function Alloc is new Alloc_On_Pool_Addr (Range_Value); begin - return To_Iir_Value_Literal_Acc - (Alloc (Current_Pool, - (Kind => Iir_Value_Range, - Left => Left, - Right => Right, - Dir => Dir, - Length => Length))); + return To_Iir_Value_Literal_Acc (Alloc (Current_Pool, + (Kind => Iir_Value_Range, + Left => Left, + Right => Right, + Dir => Dir, + Length => Length))); end Create_Range_Value; function Create_File_Value (Val : Grt.Files.Ghdl_File_Index) @@ -492,19 +490,18 @@ package body Simul.Environments is end Create_File_Value; -- Create a range_value of life LIFE. - function Create_Range_Value - (Left, Right : Iir_Value_Literal_Acc; - Dir : Iir_Direction) - return Iir_Value_Literal_Acc + function Create_Range_Value (Left, Right : Iir_Value_Literal_Acc; + Dir : Direction_Type) + return Iir_Value_Literal_Acc is Low, High : Iir_Value_Literal_Acc; Len : Iir_Index32; begin case Dir is - when Iir_To => + when Dir_To => Low := Left; High := Right; - when Iir_Downto => + when Dir_Downto => Low := Right; High := Left; end case; @@ -891,7 +888,7 @@ package body Simul.Environments is Put_Line ("range:"); Put_Indent (Indent); Put (" direction: "); - Put (Iir_Direction'Image (Value.Dir)); + Put (Direction_Type'Image (Value.Dir)); Put (", length:"); Put_Line (Iir_Index32'Image (Value.Length)); if Value.Left /= null then diff --git a/src/vhdl/simulate/simul-environments.ads b/src/vhdl/simulate/simul-environments.ads index dd0ca8b55..1d07d6bbc 100644 --- a/src/vhdl/simulate/simul-environments.ads +++ b/src/vhdl/simulate/simul-environments.ads @@ -17,6 +17,9 @@ -- 02111-1307, USA. with Ada.Unchecked_Deallocation; + +with Types; use Types; + with Vhdl.Nodes; use Vhdl.Nodes; with Vhdl.Annotations; use Vhdl.Annotations; with Grt.Types; use Grt.Types; @@ -201,7 +204,7 @@ package Simul.Environments is when Iir_Value_Instance => Instance : Block_Instance_Acc; when Iir_Value_Range => - Dir: Iir_Direction; + Dir: Direction_Type; Length : Iir_Index32; Left: Iir_Value_Literal_Acc; Right: Iir_Value_Literal_Acc; @@ -338,14 +341,14 @@ package Simul.Environments is -- Create a range_value of life LIFE. function Create_Range_Value (Left, Right : Iir_Value_Literal_Acc; - Dir : Iir_Direction; + Dir : Direction_Type; Length : Iir_Index32) return Iir_Value_Literal_Acc; -- Create a range_value (compute the length) function Create_Range_Value (Left, Right : Iir_Value_Literal_Acc; - Dir : Iir_Direction) + Dir : Direction_Type) return Iir_Value_Literal_Acc; -- Return true if the value of LEFT and RIGHT are equal. diff --git a/src/vhdl/simulate/simul-execution.adb b/src/vhdl/simulate/simul-execution.adb index a70d920c7..977921df3 100644 --- a/src/vhdl/simulate/simul-execution.adb +++ b/src/vhdl/simulate/simul-execution.adb @@ -160,9 +160,9 @@ package body Simul.Execution is R : Ghdl_E32; begin case Bounds.Dir is - when Iir_To => + when Dir_To => R := Bounds.Left.E32 + Ghdl_E32 (Len - 1); - when Iir_Downto => + when Dir_Downto => R := Bounds.Left.E32 - Ghdl_E32 (Len - 1); end case; Bounds.Right := Create_E32_Value (R); @@ -172,9 +172,9 @@ package body Simul.Execution is R : Ghdl_I64; begin case Bounds.Dir is - when Iir_To => + when Dir_To => R := Bounds.Left.I64 + Ghdl_I64 (Len - 1); - when Iir_Downto => + when Dir_Downto => R := Bounds.Left.I64 - Ghdl_I64 (Len - 1); end case; Bounds.Right := Create_I64_Value (R); @@ -205,9 +205,9 @@ package body Simul.Execution is case Res.Left.Kind is when Iir_Value_I64 => case Index_Bounds.Dir is - when Iir_To => + when Dir_To => Res.Left := Create_I64_Value (Res.Right.I64 + 1); - when Iir_Downto => + when Dir_Downto => Res.Left := Create_I64_Value (Res.Right.I64 - 1); end case; when others => @@ -222,7 +222,7 @@ package body Simul.Execution is function Execute_High_Limit (Bounds : Iir_Value_Literal_Acc) return Iir_Value_Literal_Acc is begin - if Bounds.Dir = Iir_To then + if Bounds.Dir = Dir_To then return Bounds.Right; else return Bounds.Left; @@ -232,7 +232,7 @@ package body Simul.Execution is function Execute_Low_Limit (Bounds : Iir_Value_Literal_Acc) return Iir_Value_Literal_Acc is begin - if Bounds.Dir = Iir_To then + if Bounds.Dir = Dir_To then return Bounds.Left; else return Bounds.Right; @@ -282,7 +282,7 @@ package body Simul.Execution is Res.Bounds.D (1) := Create_Range_Value (Create_I64_Value (1), Create_I64_Value (Str'Length), - Iir_To); + Dir_To); for I in Str'Range loop Res.Val_Array.V (1 + Iir_Index32 (I - Str'First)) := Create_E8_Value (Character'Pos (Str (I))); @@ -1646,14 +1646,14 @@ package body Simul.Execution is case Iir_Value_Discrete (Index.Kind) is when Iir_Value_B1 => case Bounds.Dir is - when Iir_To => + when Dir_To => if Index.B1 >= Left_Pos.B1 and then Index.B1 <= Right_Pos.B1 then -- to return Ghdl_B1'Pos (Index.B1) - Ghdl_B1'Pos (Left_Pos.B1); end if; - when Iir_Downto => + when Dir_Downto => if Index.B1 <= Left_Pos.B1 and then Index.B1 >= Right_Pos.B1 then @@ -1663,14 +1663,14 @@ package body Simul.Execution is end case; when Iir_Value_E8 => case Bounds.Dir is - when Iir_To => + when Dir_To => if Index.E8 >= Left_Pos.E8 and then Index.E8 <= Right_Pos.E8 then -- to return Iir_Index32 (Index.E8 - Left_Pos.E8); end if; - when Iir_Downto => + when Dir_Downto => if Index.E8 <= Left_Pos.E8 and then Index.E8 >= Right_Pos.E8 then @@ -1680,14 +1680,14 @@ package body Simul.Execution is end case; when Iir_Value_E32 => case Bounds.Dir is - when Iir_To => + when Dir_To => if Index.E32 >= Left_Pos.E32 and then Index.E32 <= Right_Pos.E32 then -- to return Iir_Index32 (Index.E32 - Left_Pos.E32); end if; - when Iir_Downto => + when Dir_Downto => if Index.E32 <= Left_Pos.E32 and then Index.E32 >= Right_Pos.E32 then @@ -1697,14 +1697,14 @@ package body Simul.Execution is end case; when Iir_Value_I64 => case Bounds.Dir is - when Iir_To => + when Dir_To => if Index.I64 >= Left_Pos.I64 and then Index.I64 <= Right_Pos.I64 then -- to return Iir_Index32 (Index.I64 - Left_Pos.I64); end if; - when Iir_Downto => + when Dir_Downto => if Index.I64 <= Left_Pos.I64 and then Index.I64 >= Right_Pos.I64 then @@ -1809,7 +1809,7 @@ package body Simul.Execution is Res.Bounds.D (1) := Create_Range_Value (Create_I64_Value (1), Create_I64_Value (Ghdl_I64 (Res.Val_Array.Len)), - Iir_To, + Dir_To, Res.Val_Array.Len); else Res.Bounds.D (1) := @@ -1912,7 +1912,7 @@ package body Simul.Execution is if Is_Null_Range (A_Range) then return; end if; - if A_Range.Dir = Iir_To then + if A_Range.Dir = Dir_To then High := A_Range.Right; Low := A_Range.Left; else @@ -2331,12 +2331,12 @@ package body Simul.Execution is when Iir_Kind_Reverse_Range_Array_Attribute => Bound := Execute_Indexes (Block, Prefix); case Bound.Dir is - when Iir_To => + when Dir_To => Bound := Create_Range_Value - (Bound.Right, Bound.Left, Iir_Downto, Bound.Length); - when Iir_Downto => + (Bound.Right, Bound.Left, Dir_Downto, Bound.Length); + when Dir_Downto => Bound := Create_Range_Value - (Bound.Right, Bound.Left, Iir_To, Bound.Length); + (Bound.Right, Bound.Left, Dir_To, Bound.Length); end case; when Iir_Kind_Floating_Type_Definition @@ -2616,8 +2616,8 @@ package body Simul.Execution is -- discrete range does not belong to the index range of the -- prefixing array, unless the slice is a null slice. Index_Order := Compare_Value (Srange.Left, Srange.Right); - if (Srange.Dir = Iir_To and Index_Order = Greater) - or (Srange.Dir = Iir_Downto and Index_Order = Less) + if (Srange.Dir = Dir_To and Index_Order = Greater) + or (Srange.Dir = Dir_Downto and Index_Order = Less) then -- Null slice. Low := 1; @@ -3128,7 +3128,7 @@ package body Simul.Execution is when Iir_Kind_Ascending_Array_Attribute => Res := Execute_Indexes (Block, Expr); - return Boolean_To_Lit (Res.Dir = Iir_To); + return Boolean_To_Lit (Res.Dir = Dir_To); when Iir_Kind_Event_Attribute => Res := Execute_Name (Block, Get_Prefix (Expr), True); @@ -3228,9 +3228,9 @@ package body Simul.Execution is Bound := Execute_Bounds (Block, Get_Type (Get_Prefix (Expr))); case Bound.Dir is - when Iir_To => + when Dir_To => Res := Execute_Dec (Res, Expr); - when Iir_Downto => + when Dir_Downto => Res := Execute_Inc (Res, Expr); end case; Check_Constraints (Block, Res, Get_Type (Expr), Expr); @@ -3245,9 +3245,9 @@ package body Simul.Execution is Bound := Execute_Bounds (Block, Get_Type (Get_Prefix (Expr))); case Bound.Dir is - when Iir_Downto => + when Dir_Downto => Res := Execute_Dec (Res, Expr); - when Iir_To => + when Dir_To => Res := Execute_Inc (Res, Expr); end case; Check_Constraints (Block, Res, Get_Type (Expr), Expr); @@ -3985,7 +3985,7 @@ package body Simul.Execution is | Iir_Kind_Physical_Subtype_Definition | Iir_Kind_Enumeration_Type_Definition => Bound := Execute_Bounds (Instance, Def); - if Bound.Dir = Iir_To then + if Bound.Dir = Dir_To then High := Bound.Right; Low := Bound.Left; else @@ -4373,10 +4373,10 @@ package body Simul.Execution is Max, Min : Iir_Value_Literal_Acc; begin case Bounds.Dir is - when Iir_To => + when Dir_To => Min := Bounds.Left; Max := Bounds.Right; - when Iir_Downto => + when Dir_Downto => Min := Bounds.Right; Max := Bounds.Left; end case; @@ -4402,30 +4402,30 @@ package body Simul.Execution is case Iir_Value_Discrete (Val.Kind) is when Iir_Value_E8 => case Bounds.Dir is - when Iir_To => + when Dir_To => Val.E8 := Val.E8 + 1; - when Iir_Downto => + when Dir_Downto => Val.E8 := Val.E8 - 1; end case; when Iir_Value_E32 => case Bounds.Dir is - when Iir_To => + when Dir_To => Val.E32 := Val.E32 + 1; - when Iir_Downto => + when Dir_Downto => Val.E32 := Val.E32 - 1; end case; when Iir_Value_B1 => case Bounds.Dir is - when Iir_To => + when Dir_To => Val.B1 := True; - when Iir_Downto => + when Dir_Downto => Val.B1 := False; end case; when Iir_Value_I64 => case Bounds.Dir is - when Iir_To => + when Dir_To => Val.I64 := Val.I64 + 1; - when Iir_Downto => + when Dir_Downto => Val.I64 := Val.I64 - 1; end case; end case; diff --git a/src/vhdl/simulate/simul-grt_interface.adb b/src/vhdl/simulate/simul-grt_interface.adb index e485d7d18..32e6f7b54 100644 --- a/src/vhdl/simulate/simul-grt_interface.adb +++ b/src/vhdl/simulate/simul-grt_interface.adb @@ -16,11 +16,13 @@ -- Software Foundation, 59 Temple Place - Suite 330, Boston, MA -- 02111-1307, USA. +with Types; use Types; + with Vhdl.Nodes; use Vhdl.Nodes; package body Simul.Grt_Interface is - To_Dir : constant array (Iir_Direction) of Ghdl_Dir_Type := - (Iir_To => Dir_To, Iir_Downto => Dir_Downto); + To_Dir : constant array (Direction_Type) of Ghdl_Dir_Type := + (Dir_To => Dir_To, Dir_Downto => Dir_Downto); function Build_Bound (Arr : Iir_Value_Literal_Acc) return Std_String_Bound is diff --git a/src/vhdl/translate/trans-chap14.adb b/src/vhdl/translate/trans-chap14.adb index 4618edcb1..35a3152e2 100644 --- a/src/vhdl/translate/trans-chap14.adb +++ b/src/vhdl/translate/trans-chap14.adb @@ -110,7 +110,7 @@ package body Trans.Chap14 is begin -- FIXME: improve code if constraint is a range expression. if Get_Type_Staticness (Atype) = Locally then - if Get_Direction (Cons) = Iir_To xor Is_High then + if Get_Direction (Cons) = Dir_To xor Is_High then return New_Lit (Chap7.Translate_Static_Range_Left (Cons, Atype)); else @@ -307,10 +307,10 @@ package body Trans.Chap14 is Is_Inc := False; when Iir_Kind_Leftof_Attribute => Is_Inc := - Get_Direction (Get_Range_Constraint (Prefix_Type)) = Iir_Downto; + Get_Direction (Get_Range_Constraint (Prefix_Type)) = Dir_Downto; when Iir_Kind_Rightof_Attribute => Is_Inc := - Get_Direction (Get_Range_Constraint (Prefix_Type)) = Iir_To; + Get_Direction (Get_Range_Constraint (Prefix_Type)) = Dir_To; when others => Error_Kind ("translate_succ_pred_attribute", Attr); end case; diff --git a/src/vhdl/translate/trans-chap2.adb b/src/vhdl/translate/trans-chap2.adb index 7badaeafb..84fa35a94 100644 --- a/src/vhdl/translate/trans-chap2.adb +++ b/src/vhdl/translate/trans-chap2.adb @@ -1466,7 +1466,7 @@ package body Trans.Chap2 is | Type_Iir_Pure_State | Type_Iir_Delay_Mechanism | Type_Iir_Predefined_Functions - | Type_Iir_Direction + | Type_Direction_Type | Type_Iir_Int32 | Type_Int32 | Type_Fp64 diff --git a/src/vhdl/translate/trans-chap3.adb b/src/vhdl/translate/trans-chap3.adb index b0f61fe7e..ad6207658 100644 --- a/src/vhdl/translate/trans-chap3.adb +++ b/src/vhdl/translate/trans-chap3.adb @@ -3332,9 +3332,9 @@ package body Trans.Chap3 is -- Constraint is a range expression, therefore, direction is -- known. case Get_Direction (Constr) is - when Iir_To => + when Dir_To => return Gen_Compare_To; - when Iir_Downto => + when Dir_Downto => return Gen_Compare_Downto; end case; end if; @@ -3776,18 +3776,16 @@ package body Trans.Chap3 is New_Lit (Chap7.Translate_Static_Range_Dir (Range_Constr))); case Get_Direction (Range_Constr) is - when Iir_To => + when Dir_To => Op := ON_Add_Ov; - when Iir_Downto => + when Dir_Downto => Op := ON_Sub_Ov; end case; - Start_If_Stmt - (If_Blk, - New_Compare_Op (ON_Eq, - New_Obj_Value (Length), - New_Lit (Ghdl_Index_0), - Ghdl_Bool_Type)); + Start_If_Stmt (If_Blk, New_Compare_Op (ON_Eq, + New_Obj_Value (Length), + New_Lit (Ghdl_Index_0), + Ghdl_Bool_Type)); -- Null range. New_Assign_Stmt (M2Lv (Range_To_Left (Res_Range)), diff --git a/src/vhdl/translate/trans-chap6.adb b/src/vhdl/translate/trans-chap6.adb index 433669663..ec632c815 100644 --- a/src/vhdl/translate/trans-chap6.adb +++ b/src/vhdl/translate/trans-chap6.adb @@ -232,7 +232,7 @@ package body Trans.Chap6 is Bound := M2E (Chap3.Range_To_Left (Rng)); if Deep_Rng /= Null_Iir then - if Get_Direction (Deep_Rng) = Iir_To xor Deep_Reverse then + if Get_Direction (Deep_Rng) = Dir_To xor Deep_Reverse then -- Direction TO: INDEX - LEFT. New_Assign_Stmt (New_Obj (Off), New_Dyadic_Op (ON_Sub_Ov, @@ -321,7 +321,7 @@ package body Trans.Chap6 is end if; V := Eval_Pos (Expr1); - if Get_Direction (Index_Range) = Iir_To then + if Get_Direction (Index_Range) = Dir_To then B := V - B; else B := B - V; @@ -331,7 +331,7 @@ package body Trans.Chap6 is Index_Base_Type := Get_Base_Type (Index_Type); Index := Chap7.Translate_Expression (Expr, Index_Base_Type); - if Get_Direction (Index_Range) = Iir_To then + if Get_Direction (Index_Range) = Dir_To then -- Direction TO: INDEX - LEFT. if B /= 0 then Obound := Chap7.Translate_Static_Range_Left @@ -582,9 +582,9 @@ package body Trans.Chap6 is else -- Both prefix and slice are thin array. case Get_Direction (Index_Range) is - when Iir_To => + when Dir_To => Off := Slice_Left - Prefix_Left; - when Iir_Downto => + when Dir_Downto => Off := Prefix_Left - Slice_Left; end case; if Off < 0 then @@ -672,7 +672,7 @@ package body Trans.Chap6 is New_Lit (Ghdl_Dir_To_Node), Ghdl_Bool_Type)); end if; - if not Static_Range or else Get_Direction (Expr_Range) = Iir_To then + if not Static_Range or else Get_Direction (Expr_Range) = Dir_To then -- Diff = slice - bounds. New_Assign_Stmt (New_Obj (Diff), @@ -686,7 +686,7 @@ package body Trans.Chap6 is if not Static_Range then New_Else_Stmt (If_Blk1); end if; - if not Static_Range or else Get_Direction (Expr_Range) = Iir_Downto + if not Static_Range or else Get_Direction (Expr_Range) = Dir_Downto then -- Diff = bounds - slice. New_Assign_Stmt diff --git a/src/vhdl/translate/trans-chap7.adb b/src/vhdl/translate/trans-chap7.adb index 9535b5c05..2e7e76a9b 100644 --- a/src/vhdl/translate/trans-chap7.adb +++ b/src/vhdl/translate/trans-chap7.adb @@ -639,9 +639,9 @@ package body Trans.Chap7 is function Translate_Static_Range_Dir (Expr : Iir) return O_Cnode is begin case Get_Direction (Expr) is - when Iir_To => + when Dir_To => return Ghdl_Dir_To_Node; - when Iir_Downto => + when Dir_Downto => return Ghdl_Dir_Downto_Node; end case; end Translate_Static_Range_Dir; @@ -682,7 +682,7 @@ package body Trans.Chap7 is -- Compute the length of LEFT DIR (to/downto) RIGHT. function Compute_Range_Length - (Left : O_Enode; Right : O_Enode; Dir : Iir_Direction) return O_Enode + (Left : O_Enode; Right : O_Enode; Dir : Direction_Type) return O_Enode is Rng_Type : constant O_Tnode := Ghdl_I32_Type; L : constant O_Enode := New_Convert_Ov (Left, Rng_Type); @@ -693,9 +693,9 @@ package body Trans.Chap7 is If_Blk : O_If_Block; begin case Dir is - when Iir_To => + when Dir_To => Val := New_Dyadic_Op (ON_Sub_Ov, R, L); - when Iir_Downto => + when Dir_Downto => Val := New_Dyadic_Op (ON_Sub_Ov, L, R); end case; @@ -4569,13 +4569,13 @@ package body Trans.Chap7 is return Null_Iir; end if; case Get_Direction (Rng) is - when Iir_To => + when Dir_To => if (Left_Pat = Pat_1 and Right_Pat = Pat_Length) or else (Left_Pat = Pat_0 and Right_Pat = Pat_Length_1) then return Length_Attr; end if; - when Iir_Downto => + when Dir_Downto => if (Left_Pat = Pat_Length and Right_Pat = Pat_1) or else (Left_Pat = Pat_Length_1 and Right_Pat = Pat_0) then diff --git a/src/vhdl/translate/trans-chap8.adb b/src/vhdl/translate/trans-chap8.adb index 034483c72..2c67eebd4 100644 --- a/src/vhdl/translate/trans-chap8.adb +++ b/src/vhdl/translate/trans-chap8.adb @@ -407,7 +407,7 @@ package body Trans.Chap8 is end Gen_Update_Iterator_Common; procedure Gen_Update_Iterator (Iterator : O_Dnode; - Dir : Iir_Direction; + Dir : Direction_Type; Val : Unsigned_64; Itype : Iir) is @@ -415,9 +415,9 @@ package body Trans.Chap8 is V : O_Enode; begin case Dir is - when Iir_To => + when Dir_To => Op := ON_Add_Ov; - when Iir_Downto => + when Dir_Downto => Op := ON_Sub_Ov; end case; Gen_Update_Iterator_Common (Val, Itype, V); @@ -426,7 +426,7 @@ package body Trans.Chap8 is end Gen_Update_Iterator; procedure Gen_Update_Iterator (Iterator : Var_Type; - Dir : Iir_Direction; + Dir : Direction_Type; Val : Unsigned_64; Itype : Iir) is @@ -434,9 +434,9 @@ package body Trans.Chap8 is V : O_Enode; begin case Dir is - when Iir_To => + when Dir_To => Op := ON_Add_Ov; - when Iir_Downto => + when Dir_Downto => Op := ON_Sub_Ov; end case; Gen_Update_Iterator_Common (Val, Itype, V); @@ -550,7 +550,7 @@ package body Trans.Chap8 is Iter_Type_Info : constant Ortho_Info_Acc := Get_Info (Iter_Base_Type); It_Info : constant Ortho_Info_Acc := Get_Info (Iterator); Constraint : constant Iir := Get_Range_Constraint (Iter_Type); - Dir : Iir_Direction; + Dir : Direction_Type; Op : ON_Op_Kind; Rng : O_Lnode; begin @@ -565,9 +565,9 @@ package body Trans.Chap8 is Chap7.Translate_Range_Expression_Right (Constraint, Iter_Base_Type)); case Dir is - when Iir_To => + when Dir_To => Op := ON_Le; - when Iir_Downto => + when Dir_Downto => Op := ON_Ge; end case; -- Check for at least one iteration. @@ -632,12 +632,12 @@ package body Trans.Chap8 is -- Update the iterator. Chap6.Get_Deep_Range_Expression (Iter_Type, Deep_Rng, Deep_Reverse); if Deep_Rng /= Null_Iir then - if Get_Direction (Deep_Rng) = Iir_To xor Deep_Reverse then + if Get_Direction (Deep_Rng) = Dir_To xor Deep_Reverse then Gen_Update_Iterator (It_Info.Iterator_Var, - Iir_To, 1, Iter_Base_Type); + Dir_To, 1, Iter_Base_Type); else Gen_Update_Iterator (It_Info.Iterator_Var, - Iir_Downto, 1, Iter_Base_Type); + Dir_Downto, 1, Iter_Base_Type); end if; else Start_If_Stmt @@ -647,10 +647,10 @@ package body Trans.Chap8 is New_Lit (Ghdl_Dir_To_Node), Ghdl_Bool_Type)); Gen_Update_Iterator (It_Info.Iterator_Var, - Iir_To, 1, Iter_Base_Type); + Dir_To, 1, Iter_Base_Type); New_Else_Stmt (If_Blk1); Gen_Update_Iterator (It_Info.Iterator_Var, - Iir_Downto, 1, Iter_Base_Type); + Dir_Downto, 1, Iter_Base_Type); Finish_If_Stmt (If_Blk1); end if; end Update_For_Loop; diff --git a/src/vhdl/translate/trans-chap8.ads b/src/vhdl/translate/trans-chap8.ads index 8a230ce82..9433f865b 100644 --- a/src/vhdl/translate/trans-chap8.ads +++ b/src/vhdl/translate/trans-chap8.ads @@ -78,7 +78,7 @@ package Trans.Chap8 is -- Inc or dec by VAL ITERATOR according to DIR. -- Used for loop statements. procedure Gen_Update_Iterator (Iterator : O_Dnode; - Dir : Iir_Direction; + Dir : Direction_Type; Val : Unsigned_64; Itype : Iir); diff --git a/src/vhdl/translate/trans-chap9.adb b/src/vhdl/translate/trans-chap9.adb index 58533e37b..5ec57edc7 100644 --- a/src/vhdl/translate/trans-chap9.adb +++ b/src/vhdl/translate/trans-chap9.adb @@ -1383,7 +1383,7 @@ package body Trans.Chap9 is | Type_Iir_Pure_State | Type_Iir_Delay_Mechanism | Type_Iir_Predefined_Functions - | Type_Iir_Direction + | Type_Direction_Type | Type_Iir_Int32 | Type_Int32 | Type_Fp64 diff --git a/src/vhdl/vhdl-disp_tree.adb b/src/vhdl/vhdl-disp_tree.adb index 16aaab9f8..b9801ce89 100644 --- a/src/vhdl/vhdl-disp_tree.adb +++ b/src/vhdl/vhdl-disp_tree.adb @@ -328,15 +328,15 @@ package body Vhdl.Disp_Tree is return Files_Map.Image (Loc); end Image_Location_Type; - function Image_Iir_Direction (Dir : Iir_Direction) return String is + function Image_Direction_Type (Dir : Direction_Type) return String is begin case Dir is - when Iir_To => + when Dir_To => return "to"; - when Iir_Downto => + when Dir_Downto => return "downto"; end case; - end Image_Iir_Direction; + end Image_Direction_Type; function Image_Token_Type (Tok : Vhdl.Tokens.Token_Type) return String renames Vhdl.Tokens.Image; @@ -574,9 +574,9 @@ package body Vhdl.Disp_Tree is when Type_Iir_Predefined_Functions => Log_Line (Image_Iir_Predefined_Functions (Get_Iir_Predefined_Functions (N, F))); - when Type_Iir_Direction => - Log_Line (Image_Iir_Direction - (Get_Iir_Direction (N, F))); + when Type_Direction_Type => + Log_Line (Image_Direction_Type + (Get_Direction_Type (N, F))); when Type_Iir_Int32 => Log_Line (Iir_Int32'Image (Get_Iir_Int32 (N, F))); when Type_Int32 => diff --git a/src/vhdl/vhdl-disp_tree.ads b/src/vhdl/vhdl-disp_tree.ads index 633844d38..3dcf8bd1b 100644 --- a/src/vhdl/vhdl-disp_tree.ads +++ b/src/vhdl/vhdl-disp_tree.ads @@ -47,7 +47,7 @@ package Vhdl.Disp_Tree is function Image_Iir_Predefined_Functions (F : Iir_Predefined_Functions) return String; function Image_Location_Type (Loc : Location_Type) return String; - function Image_Iir_Direction (Dir : Iir_Direction) return String; + function Image_Direction_Type (Dir : Direction_Type) return String; function Image_Token_Type (Tok : Vhdl.Tokens.Token_Type) return String; function Image_String8 (N : Iir) return String; function Image_Scalar_Size (Sz : Scalar_Size) return String; diff --git a/src/vhdl/vhdl-evaluation.adb b/src/vhdl/vhdl-evaluation.adb index 9ffe40b42..e33c2bea4 100644 --- a/src/vhdl/vhdl-evaluation.adb +++ b/src/vhdl/vhdl-evaluation.adb @@ -328,9 +328,9 @@ package body Vhdl.Evaluation is Pos := Eval_Pos (Left); case Get_Direction (A_Range) is - when Iir_To => + when Dir_To => Pos := Pos + Len - 1; - when Iir_Downto => + when Dir_Downto => Pos := Pos - Len + 1; end case; if Len > 0 @@ -489,9 +489,9 @@ package body Vhdl.Evaluation is Pos : constant Int64 := Eval_Pos (Expr); begin case Get_Direction (Rng) is - when Iir_To => + when Dir_To => return Iir_Index32 (Pos - Left_Pos); - when Iir_Downto => + when Dir_Downto => return Iir_Index32 (Left_Pos - Pos); end case; end Eval_Pos_In_Range; @@ -2457,9 +2457,9 @@ package body Vhdl.Evaluation is when Iir_Kind_Choice_By_None => exit when Cur_Pos = Eval_Pos (Idx); case Get_Direction (Aggr_Bounds) is - when Iir_To => + when Dir_To => Cur_Pos := Cur_Pos + 1; - when Iir_Downto => + when Dir_Downto => Cur_Pos := Cur_Pos - 1; end case; when Iir_Kind_Choice_By_Expression => @@ -2614,9 +2614,9 @@ package body Vhdl.Evaluation is when Iir_Kind_Choice_By_Expression => Assoc_Pos := Eval_Pos (Get_Choice_Expression (Assoc)); case Get_Direction (Aggr_Bounds) is - when Iir_To => + when Dir_To => Cur_Off := Iir_Index32 (Assoc_Pos - Left_Pos); - when Iir_Downto => + when Dir_Downto => Cur_Off := Iir_Index32 (Left_Pos - Assoc_Pos); end case; if Cur_Off = Off then @@ -2636,18 +2636,18 @@ package body Vhdl.Evaluation is Left := Eval_Pos (Get_Left_Limit (Rng)); Right := Eval_Pos (Get_Right_Limit (Rng)); case Get_Direction (Rng) is - when Iir_To => + when Dir_To => Lo := Left; Hi := Right; - when Iir_Downto => + when Dir_Downto => Lo := Right; Hi := Left; end case; case Get_Direction (Aggr_Bounds) is - when Iir_To => + when Dir_To => Lo_Off := Iir_Index32 (Lo - Left_Pos); Hi_Off := Iir_Index32 (Hi - Left_Pos); - when Iir_Downto => + when Dir_Downto => Lo_Off := Iir_Index32 (Left_Pos - Lo); Hi_Off := Iir_Index32 (Left_Pos - Hi); end case; @@ -2900,7 +2900,7 @@ package body Vhdl.Evaluation is (Get_Low_Limit (Eval_Static_Range (Get_Prefix (Expr)))); when Iir_Kind_Ascending_Type_Attribute => return Build_Boolean - (Get_Direction (Eval_Static_Range (Get_Prefix (Expr))) = Iir_To); + (Get_Direction (Eval_Static_Range (Get_Prefix (Expr))) = Dir_To); when Iir_Kind_Length_Array_Attribute => declare @@ -2947,7 +2947,7 @@ package body Vhdl.Evaluation is begin Index := Eval_Array_Attribute (Expr); return Build_Boolean - (Get_Direction (Get_Range_Constraint (Index)) = Iir_To); + (Get_Direction (Get_Range_Constraint (Index)) = Dir_To); end; when Iir_Kind_Pred_Attribute => @@ -2970,9 +2970,9 @@ package body Vhdl.Evaluation is begin Rng := Eval_Static_Range (Prefix_Type); case Get_Direction (Rng) is - when Iir_To => + when Dir_To => N := 1; - when Iir_Downto => + when Dir_Downto => N := -1; end case; case Get_Kind (Expr) is @@ -3270,13 +3270,13 @@ package body Vhdl.Evaluation is case Get_Kind (Bound) is when Iir_Kind_Range_Expression => case Get_Direction (Bound) is - when Iir_To => + when Dir_To => if Val < Eval_Pos (Get_Left_Limit (Bound)) or else Val > Eval_Pos (Get_Right_Limit (Bound)) then return False; end if; - when Iir_Downto => + when Dir_Downto => if Val > Eval_Pos (Get_Left_Limit (Bound)) or else Val < Eval_Pos (Get_Right_Limit (Bound)) then @@ -3308,11 +3308,11 @@ package body Vhdl.Evaluation is Error_Kind ("eval_phys_in_range(1)", Get_Type (Bound)); end case; case Get_Direction (Bound) is - when Iir_To => + when Dir_To => if Val < Left or else Val > Right then return False; end if; - when Iir_Downto => + when Dir_Downto => if Val > Left or else Val < Right then return False; end if; @@ -3328,13 +3328,13 @@ package body Vhdl.Evaluation is case Get_Kind (Bound) is when Iir_Kind_Range_Expression => case Get_Direction (Bound) is - when Iir_To => + when Dir_To => if Val < Get_Fp_Value (Get_Left_Limit (Bound)) or else Val > Get_Fp_Value (Get_Right_Limit (Bound)) then return False; end if; - when Iir_Downto => + when Dir_Downto => if Val > Get_Fp_Value (Get_Left_Limit (Bound)) or else Val < Get_Fp_Value (Get_Right_Limit (Bound)) then @@ -3530,11 +3530,11 @@ package body Vhdl.Evaluation is L := Eval_Pos (Get_Left_Limit (Range_Constraint)); R := Eval_Pos (Get_Right_Limit (Range_Constraint)); case Get_Direction (Range_Constraint) is - when Iir_To => + when Dir_To => if L > R then return True; end if; - when Iir_Downto => + when Dir_Downto => if L < R then return True; end if; @@ -3550,11 +3550,11 @@ package body Vhdl.Evaluation is L := Get_Fp_Value (Get_Left_Limit (Range_Constraint)); R := Get_Fp_Value (Get_Right_Limit (Range_Constraint)); case Get_Direction (Range_Constraint) is - when Iir_To => + when Dir_To => if L > R then return True; end if; - when Iir_Downto => + when Dir_Downto => if L < R then return True; end if; @@ -3590,14 +3590,14 @@ package body Vhdl.Evaluation is Left := Eval_Pos (Get_Left_Limit (Constraint)); Right := Eval_Pos (Get_Right_Limit (Constraint)); case Get_Direction (Constraint) is - when Iir_To => + when Dir_To => if Right < Left then -- Null range. return 0; else Res := Right - Left + 1; end if; - when Iir_Downto => + when Dir_Downto => if Left < Right then -- Null range return 0; @@ -3629,9 +3629,9 @@ package body Vhdl.Evaluation is Left := Eval_Pos (Get_Left_Limit (Rng)); Right := Eval_Pos (Get_Right_Limit (Rng)); case Get_Direction (Rng) is - when Iir_To => + when Dir_To => return Right < Left; - when Iir_Downto => + when Dir_Downto => return Left < Right; end case; end Eval_Is_Null_Discrete_Range; @@ -3727,10 +3727,10 @@ package body Vhdl.Evaluation is Location_Copy (Res, Expr); Set_Type (Res, Get_Type (Expr)); case Get_Direction (Expr) is - when Iir_To => - Set_Direction (Res, Iir_Downto); - when Iir_Downto => - Set_Direction (Res, Iir_To); + when Dir_To => + Set_Direction (Res, Dir_Downto); + when Dir_Downto => + Set_Direction (Res, Dir_To); end case; Set_Left_Limit (Res, Get_Right_Limit (Expr)); Set_Right_Limit (Res, Get_Left_Limit (Expr)); diff --git a/src/vhdl/vhdl-nodes.adb b/src/vhdl/vhdl-nodes.adb index 21697e6b1..44d5eb157 100644 --- a/src/vhdl/vhdl-nodes.adb +++ b/src/vhdl/vhdl-nodes.adb @@ -3670,20 +3670,20 @@ package body Vhdl.Nodes is Set_Field1 (Target, Constraint); end Set_Range_Constraint; - function Get_Direction (Decl : Iir) return Iir_Direction is + function Get_Direction (Decl : Iir) return Direction_Type is begin pragma Assert (Decl /= Null_Iir); pragma Assert (Has_Direction (Get_Kind (Decl)), "no field Direction"); - return Iir_Direction'Val (Get_State2 (Decl)); + return Direction_Type'Val (Get_State2 (Decl)); end Get_Direction; - procedure Set_Direction (Decl : Iir; Dir : Iir_Direction) is + procedure Set_Direction (Decl : Iir; Dir : Direction_Type) is begin pragma Assert (Decl /= Null_Iir); pragma Assert (Has_Direction (Get_Kind (Decl)), "no field Direction"); - Set_State2 (Decl, Iir_Direction'Pos (Dir)); + Set_State2 (Decl, Direction_Type'Pos (Dir)); end Set_Direction; function Get_Left_Limit (Decl : Iir_Range_Expression) return Iir is diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 5d50057e4..592a7da2a 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5083,12 +5083,6 @@ package Vhdl.Nodes is Iir_Transport_Delay ); - type Iir_Direction is - ( - Iir_To, - Iir_Downto - ); - -- LRM93 2.7 (conformance rules). -- To keep this simple, the layout is stored as a bit-string. -- Fields are: @@ -7860,8 +7854,8 @@ package Vhdl.Nodes is procedure Set_Range_Constraint (Target : Iir; Constraint : Iir); -- Field: State2 (pos) - function Get_Direction (Decl : Iir) return Iir_Direction; - procedure Set_Direction (Decl : Iir; Dir : Iir_Direction); + function Get_Direction (Decl : Iir) return Direction_Type; + procedure Set_Direction (Decl : Iir; Dir : Direction_Type); -- Field: Field4 Ref function Get_Left_Limit (Decl : Iir_Range_Expression) return Iir; diff --git a/src/vhdl/vhdl-nodes_meta.adb b/src/vhdl/vhdl-nodes_meta.adb index 1046e8856..0b4987502 100644 --- a/src/vhdl/vhdl-nodes_meta.adb +++ b/src/vhdl/vhdl-nodes_meta.adb @@ -162,7 +162,7 @@ package body Vhdl.Nodes_Meta is Field_Label => Type_Name_Id, Field_Visible_Flag => Type_Boolean, Field_Range_Constraint => Type_Iir, - Field_Direction => Type_Iir_Direction, + Field_Direction => Type_Direction_Type, Field_Left_Limit => Type_Iir, Field_Right_Limit => Type_Iir, Field_Left_Limit_Expr => Type_Iir, @@ -5737,6 +5737,30 @@ package body Vhdl.Nodes_Meta is end case; end Set_Date_Type; + function Get_Direction_Type + (N : Iir; F : Fields_Enum) return Direction_Type is + begin + pragma Assert (Fields_Type (F) = Type_Direction_Type); + case F is + when Field_Direction => + return Get_Direction (N); + when others => + raise Internal_Error; + end case; + end Get_Direction_Type; + + procedure Set_Direction_Type + (N : Iir; F : Fields_Enum; V: Direction_Type) is + begin + pragma Assert (Fields_Type (F) = Type_Direction_Type); + case F is + when Field_Direction => + Set_Direction (N, V); + when others => + raise Internal_Error; + end case; + end Set_Direction_Type; + function Get_File_Checksum_Id (N : Iir; F : Fields_Enum) return File_Checksum_Id is begin @@ -6753,30 +6777,6 @@ package body Vhdl.Nodes_Meta is end case; end Set_Iir_Delay_Mechanism; - function Get_Iir_Direction - (N : Iir; F : Fields_Enum) return Iir_Direction is - begin - pragma Assert (Fields_Type (F) = Type_Iir_Direction); - case F is - when Field_Direction => - return Get_Direction (N); - when others => - raise Internal_Error; - end case; - end Get_Iir_Direction; - - procedure Set_Iir_Direction - (N : Iir; F : Fields_Enum; V: Iir_Direction) is - begin - pragma Assert (Fields_Type (F) = Type_Iir_Direction); - case F is - when Field_Direction => - Set_Direction (N, V); - when others => - raise Internal_Error; - end case; - end Set_Iir_Direction; - function Get_Iir_Flist (N : Iir; F : Fields_Enum) return Iir_Flist is begin diff --git a/src/vhdl/vhdl-nodes_meta.ads b/src/vhdl/vhdl-nodes_meta.ads index dd48460d8..bb0b4e102 100644 --- a/src/vhdl/vhdl-nodes_meta.ads +++ b/src/vhdl/vhdl-nodes_meta.ads @@ -28,13 +28,13 @@ package Vhdl.Nodes_Meta is Type_Boolean, Type_Date_State_Type, Type_Date_Type, + Type_Direction_Type, Type_File_Checksum_Id, Type_Fp64, Type_Iir, Type_Iir_All_Sensitized, Type_Iir_Constraint, Type_Iir_Delay_Mechanism, - Type_Iir_Direction, Type_Iir_Flist, Type_Iir_Index32, Type_Iir_Int32, @@ -483,6 +483,11 @@ package Vhdl.Nodes_Meta is procedure Set_Date_Type (N : Iir; F : Fields_Enum; V: Date_Type); + function Get_Direction_Type + (N : Iir; F : Fields_Enum) return Direction_Type; + procedure Set_Direction_Type + (N : Iir; F : Fields_Enum; V: Direction_Type); + function Get_File_Checksum_Id (N : Iir; F : Fields_Enum) return File_Checksum_Id; procedure Set_File_Checksum_Id @@ -513,11 +518,6 @@ package Vhdl.Nodes_Meta is procedure Set_Iir_Delay_Mechanism (N : Iir; F : Fields_Enum; V: Iir_Delay_Mechanism); - function Get_Iir_Direction - (N : Iir; F : Fields_Enum) return Iir_Direction; - procedure Set_Iir_Direction - (N : Iir; F : Fields_Enum; V: Iir_Direction); - function Get_Iir_Flist (N : Iir; F : Fields_Enum) return Iir_Flist; procedure Set_Iir_Flist diff --git a/src/vhdl/vhdl-parse.adb b/src/vhdl/vhdl-parse.adb index a625294a5..f6d21731a 100644 --- a/src/vhdl/vhdl-parse.adb +++ b/src/vhdl/vhdl-parse.adb @@ -597,9 +597,9 @@ package body Vhdl.Parse is case Current_Token is when Tok_To => - Set_Direction (Res, Iir_To); + Set_Direction (Res, Dir_To); when Tok_Downto => - Set_Direction (Res, Iir_Downto); + Set_Direction (Res, Dir_Downto); when others => raise Internal_Error; end case; diff --git a/src/vhdl/vhdl-prints.adb b/src/vhdl/vhdl-prints.adb index f1d2d7a79..b3bef235c 100644 --- a/src/vhdl/vhdl-prints.adb +++ b/src/vhdl/vhdl-prints.adb @@ -322,7 +322,7 @@ package body Vhdl.Prints is else Print (Ctxt, Or_Else (Get_Left_Limit_Expr (Rng), Get_Left_Limit (Rng))); - if Get_Direction (Rng) = Iir_To then + if Get_Direction (Rng) = Dir_To then Disp_Token (Ctxt, Tok_To); else Disp_Token (Ctxt, Tok_Downto); diff --git a/src/vhdl/vhdl-sem_assocs.adb b/src/vhdl/vhdl-sem_assocs.adb index d68c4812e..20b8f5c09 100644 --- a/src/vhdl/vhdl-sem_assocs.adb +++ b/src/vhdl/vhdl-sem_assocs.adb @@ -968,12 +968,12 @@ package body Vhdl.Sem_Assocs is High := Copy_Constant (High); case Get_Direction (Index_Constraint) is - when Iir_To => + when Dir_To => Set_Left_Limit (Index_Subtype_Constraint, Low); Set_Left_Limit_Expr (Index_Subtype_Constraint, Low); Set_Right_Limit (Index_Subtype_Constraint, High); Set_Right_Limit_Expr (Index_Subtype_Constraint, High); - when Iir_Downto => + when Dir_Downto => Set_Left_Limit (Index_Subtype_Constraint, High); Set_Left_Limit_Expr (Index_Subtype_Constraint, High); Set_Right_Limit (Index_Subtype_Constraint, Low); diff --git a/src/vhdl/vhdl-sem_expr.adb b/src/vhdl/vhdl-sem_expr.adb index 3f34ccf10..e9f05f9bc 100644 --- a/src/vhdl/vhdl-sem_expr.adb +++ b/src/vhdl/vhdl-sem_expr.adb @@ -3431,7 +3431,7 @@ package body Vhdl.Sem_Expr is Index_Subtype_Constraint : Iir_Range_Expression; Index_Constraint : Iir_Range_Expression; -- FIXME: 'range. - Dir : Iir_Direction; + Dir : Direction_Type; Choice_Staticness : Iir_Staticness; Len_Staticness : Iir_Staticness; Expr_Staticness : Iir_Staticness; @@ -3708,7 +3708,7 @@ package body Vhdl.Sem_Expr is -- at analysis time (if 'Range), and it doesn't really matter -- because of implicit subtype conversion. So choose one -- arbitrary direction. - Dir := Iir_To; + Dir := Dir_To; end if; -- LRM93 7.3.2.2 @@ -3725,10 +3725,10 @@ package body Vhdl.Sem_Expr is else Set_Direction (Index_Subtype_Constraint, Dir); case Dir is - when Iir_To => + when Dir_To => Set_Left_Limit (Index_Subtype_Constraint, Low); Set_Right_Limit (Index_Subtype_Constraint, High); - when Iir_Downto => + when Dir_Downto => Set_Left_Limit (Index_Subtype_Constraint, High); Set_Right_Limit (Index_Subtype_Constraint, Low); end case; diff --git a/src/vhdl/vhdl-sem_inst.adb b/src/vhdl/vhdl-sem_inst.adb index 186c573e8..418b3f998 100644 --- a/src/vhdl/vhdl-sem_inst.adb +++ b/src/vhdl/vhdl-sem_inst.adb @@ -371,8 +371,8 @@ package body Vhdl.Sem_Inst is when Type_Iir_Predefined_Functions => Set_Iir_Predefined_Functions (Res, F, Get_Iir_Predefined_Functions (N, F)); - when Type_Iir_Direction => - Set_Iir_Direction (Res, F, Get_Iir_Direction (N, F)); + when Type_Direction_Type => + Set_Direction_Type (Res, F, Get_Direction_Type (N, F)); when Type_Iir_Int32 => Set_Iir_Int32 (Res, F, Get_Iir_Int32 (N, F)); when Type_Int32 => diff --git a/src/vhdl/vhdl-sem_types.adb b/src/vhdl/vhdl-sem_types.adb index f13010dee..7ea08eab9 100644 --- a/src/vhdl/vhdl-sem_types.adb +++ b/src/vhdl/vhdl-sem_types.adb @@ -162,12 +162,12 @@ package body Vhdl.Sem_Types is if Get_Kind (Left) = Iir_Kind_Overflow_Literal then Error_Msg_Sem (+Left, "overflow in left bound"); Left := Build_Extreme_Value - (Get_Direction (Expr) = Iir_Downto, Left); + (Get_Direction (Expr) = Dir_Downto, Left); end if; if Get_Kind (Right) = Iir_Kind_Overflow_Literal then Error_Msg_Sem (+Right, "overflow in right bound"); Right := Build_Extreme_Value - (Get_Direction (Expr) = Iir_To, Right); + (Get_Direction (Expr) = Dir_To, Right); end if; Set_Left_Limit_Expr (Expr, Left); Set_Right_Limit_Expr (Expr, Right); diff --git a/src/vhdl/vhdl-std_package.adb b/src/vhdl/vhdl-std_package.adb index 1495de4cf..c5c029a4c 100644 --- a/src/vhdl/vhdl-std_package.adb +++ b/src/vhdl/vhdl-std_package.adb @@ -153,7 +153,7 @@ package body Vhdl.Std_Package is Res := Create_Std_Iir (Iir_Kind_Range_Expression); Set_Left_Limit (Res, Left); Set_Left_Limit_Expr (Res, Left); - Set_Direction (Res, Iir_To); + Set_Direction (Res, Dir_To); Set_Right_Limit (Res, Right); Set_Right_Limit_Expr (Res, Right); Set_Expr_Staticness (Res, Locally); diff --git a/src/vhdl/vhdl-utils.adb b/src/vhdl/vhdl-utils.adb index 461f301f4..029baa3ca 100644 --- a/src/vhdl/vhdl-utils.adb +++ b/src/vhdl/vhdl-utils.adb @@ -794,7 +794,7 @@ package body Vhdl.Utils is Range_Expr := Create_Iir (Iir_Kind_Range_Expression); Location_Copy (Range_Expr, Def); Set_Type (Range_Expr, Def); - Set_Direction (Range_Expr, Iir_To); + Set_Direction (Range_Expr, Dir_To); if List_Len >= 1 then Set_Left_Limit (Range_Expr, Get_Nth_Element (Literal_List, 0)); @@ -1485,10 +1485,10 @@ package body Vhdl.Utils is is begin case Get_Direction (Arange) is - when Iir_To => + when Dir_To => Low := Get_Left_Limit (Arange); High := Get_Right_Limit (Arange); - when Iir_Downto => + when Dir_Downto => High := Get_Left_Limit (Arange); Low := Get_Right_Limit (Arange); end case; @@ -1497,9 +1497,9 @@ package body Vhdl.Utils is function Get_Low_Limit (Arange : Iir_Range_Expression) return Iir is begin case Get_Direction (Arange) is - when Iir_To => + when Dir_To => return Get_Left_Limit (Arange); - when Iir_Downto => + when Dir_Downto => return Get_Right_Limit (Arange); end case; end Get_Low_Limit; @@ -1507,9 +1507,9 @@ package body Vhdl.Utils is function Get_High_Limit (Arange : Iir_Range_Expression) return Iir is begin case Get_Direction (Arange) is - when Iir_To => + when Dir_To => return Get_Right_Limit (Arange); - when Iir_Downto => + when Dir_Downto => return Get_Left_Limit (Arange); end case; end Get_High_Limit; |