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| author | Tristan Gingold <tgingold@free.fr> | 2019-07-01 06:27:18 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-07-01 06:27:18 +0200 |
| commit | c428e11471d4323632305d0b8a665262af6a9a60 (patch) | |
| tree | 0f3d3b55e930d0a3fe635eb02187897e4b6c4112 | |
| parent | 5c89355a7d8781a7a5138d3c141d62cd9f8ccb2f (diff) | |
| download | ghdl-c428e11471d4323632305d0b8a665262af6a9a60.tar.gz ghdl-c428e11471d4323632305d0b8a665262af6a9a60.tar.bz2 ghdl-c428e11471d4323632305d0b8a665262af6a9a60.zip | |
netlists disp_vhdl: rewrite uextend.
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 0f7418167..701d1f782 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -524,12 +524,14 @@ package body Netlists.Disp_Vhdl is end; when Id_Uextend => declare - W : constant Width := Get_Width (Get_Output (Inst, 0)); + Ow : constant Width := Get_Width (Get_Output (Inst, 0)); + Iw : constant Width := Get_Width (Get_Input_Net (Inst, 0)); begin - Disp_Template (" \o0 <= std_logic_vector (resize (\ui0, ", - Inst); - Put_Uns32 (W); - Put_Line ("));"); + pragma Assert (Iw > 0); + pragma Assert (Ow > Iw); + Disp_Template (" \o0 <= """, Inst); + Put ((1 .. Natural (Ow - Iw) => '0')); + Disp_Template (""" & \i0; -- uext" & NL, Inst); end; when others => Disp_Instance_Gate (Inst); |