synth-environment: add Loc parameter to Add_Conc_Assign

3 files changed, 13 insertions, 4 deletions

diff --git a/src/synth/synth-environment.adb b/src/synth/synth-environment.adb
index 7e809e7cc..ccc1e8c58 100644
--- a/src/synth/synth-environment.adb
+++ b/src/synth/synth-environment.adb
@@ -380,12 +380,14 @@ package body Synth.Environment is
       Conc_Assign_Table.Table (Asgn).Next := Chain;
    end Set_Conc_Chain;
 
-   procedure Add_Conc_Assign (Wid : Wire_Id; Val : Net; Off : Uns32)
+   procedure Add_Conc_Assign
+     (Wid : Wire_Id; Val : Net; Off : Uns32; Loc : Location_Type)
    is
       Wire_Rec : Wire_Id_Record renames Wire_Id_Table.Table (Wid);
    begin
       pragma Assert (Wire_Rec.Kind /= Wire_None);
       Conc_Assign_Table.Append ((Next => Wire_Rec.Final_Assign,
+                                 Loc => Loc,
                                  Value => Val,
                                  Offset => Off));
       Wire_Rec.Final_Assign := Conc_Assign_Table.Last;
@@ -416,7 +418,7 @@ package body Synth.Environment is
             if Wire_Rec.Kind = Wire_Enable then
                Connect (Get_Input (Get_Net_Parent (Outport), 0), Res);
             else
-               Add_Conc_Assign (Wid, Res, 0);
+               Add_Conc_Assign (Wid, Res, 0, Loc);
             end if;
          when False =>
             P := Asgn_Rec.Val.Asgns;
@@ -838,6 +840,7 @@ package body Synth.Environment is
             --  FIXME: handle initial values.
             Conc_Assign_Table.Append
               ((Next => Asgn,
+                Loc => No_Location,
                 Value => Build_Const_Z (Ctxt, Next_Off - Expected_Off),
                 Offset => Expected_Off));
             New_Asgn := Conc_Assign_Table.Last;
@@ -2032,6 +2035,7 @@ begin
    pragma Assert (Phis_Table.Last = No_Phi_Id);
 
    Conc_Assign_Table.Append ((Next => No_Conc_Assign,
+                              Loc => No_Location,
                               Value => No_Net,
                               Offset => 0));
    pragma Assert (Conc_Assign_Table.Last = No_Conc_Assign);
diff --git a/src/synth/synth-environment.ads b/src/synth/synth-environment.ads
index 604ca0caf..b3372e96f 100644
--- a/src/synth/synth-environment.ads
+++ b/src/synth/synth-environment.ads
@@ -276,7 +276,9 @@ package Synth.Environment is
    type Conc_Assign is private;
    No_Conc_Assign : constant Conc_Assign;
 
-   procedure Add_Conc_Assign (Wid : Wire_Id; Val : Net; Off : Uns32);
+   --  Add a concurrent assignment to WID.
+   procedure Add_Conc_Assign
+     (Wid : Wire_Id; Val : Net; Off : Uns32; Loc : Location_Type);
 
    procedure Finalize_Assignment
      (Ctxt : Builders.Context_Acc; Wid : Wire_Id);
@@ -375,6 +377,9 @@ private
    type Conc_Assign_Record is record
       Next : Conc_Assign;
 
+      --  Location of the assignment.
+      Loc : Location_Type;
+
       --  Concurrent assignment at OFFSET.  The width is set by value width.
       Value : Net;
       Offset : Uns32;
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb
index f351c34f3..7d0c0b805 100644
--- a/src/synth/synth-vhdl_stmts.adb
+++ b/src/synth/synth-vhdl_stmts.adb
@@ -3871,7 +3871,7 @@ package body Synth.Vhdl_Stmts is
 
          N := Build_Formal_Input (Get_Build (Syn_Inst), Id, Typ.W);
          Set_Location (N, Val);
-         Add_Conc_Assign (Get_Value_Wire (Base.Val), N, 0);
+         Add_Conc_Assign (Get_Value_Wire (Base.Val), N, 0, Get_Location (Val));
       end;
    end Synth_Attribute_Formal;