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author | Tristan Gingold <tgingold@free.fr> | 2020-03-10 20:42:02 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-03-10 20:42:02 +0100 |
commit | be40560c399be55a0145feec81a07fa89bf6704f (patch) | |
tree | 745c592bcd93eb9733e55a4dcced4e630518bf87 | |
parent | 63e0082aa92df57f99347ace07b706b51b7fd4c9 (diff) | |
download | ghdl-be40560c399be55a0145feec81a07fa89bf6704f.tar.gz ghdl-be40560c399be55a0145feec81a07fa89bf6704f.tar.bz2 ghdl-be40560c399be55a0145feec81a07fa89bf6704f.zip |
testsuite/synth: add tests for previous commit.
-rw-r--r-- | testsuite/synth/oper02/max01.vhdl | 9 | ||||
-rw-r--r-- | testsuite/synth/oper02/min01.vhdl | 9 | ||||
-rw-r--r-- | testsuite/synth/oper02/tb_max01.vhdl | 26 | ||||
-rw-r--r-- | testsuite/synth/oper02/tb_min01.vhdl | 26 | ||||
-rwxr-xr-x | testsuite/synth/oper02/testsuite.sh | 10 |
5 files changed, 80 insertions, 0 deletions
diff --git a/testsuite/synth/oper02/max01.vhdl b/testsuite/synth/oper02/max01.vhdl new file mode 100644 index 000000000..4fe63ddd1 --- /dev/null +++ b/testsuite/synth/oper02/max01.vhdl @@ -0,0 +1,9 @@ +entity max01 is + port (a, b : natural; + o : out natural); +end max01; + +architecture behav of max01 is +begin + o <= maximum (a, b); +end behav; diff --git a/testsuite/synth/oper02/min01.vhdl b/testsuite/synth/oper02/min01.vhdl new file mode 100644 index 000000000..1a90db24d --- /dev/null +++ b/testsuite/synth/oper02/min01.vhdl @@ -0,0 +1,9 @@ +entity min01 is + port (a, b : natural; + o : out natural); +end min01; + +architecture behav of min01 is +begin + o <= minimum (a, b); +end behav; diff --git a/testsuite/synth/oper02/tb_max01.vhdl b/testsuite/synth/oper02/tb_max01.vhdl new file mode 100644 index 000000000..d5a458034 --- /dev/null +++ b/testsuite/synth/oper02/tb_max01.vhdl @@ -0,0 +1,26 @@ +entity tb_max01 is +end tb_max01; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_max01 is + signal l, r : natural; + signal res : natural; +begin + max01_1: entity work.max01 + port map ( + a => l, + b => r, + o => res); + + process + begin + l <= 12; + r <= 15; + wait for 1 ns; + assert res = 15 severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/oper02/tb_min01.vhdl b/testsuite/synth/oper02/tb_min01.vhdl new file mode 100644 index 000000000..b0fd6c234 --- /dev/null +++ b/testsuite/synth/oper02/tb_min01.vhdl @@ -0,0 +1,26 @@ +entity tb_min01 is +end tb_min01; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_min01 is + signal l, r : natural; + signal res : natural; +begin + min01_1: entity work.min01 + port map ( + a => l, + b => r, + o => res); + + process + begin + l <= 12; + r <= 15; + wait for 1 ns; + assert res = 12 severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/oper02/testsuite.sh b/testsuite/synth/oper02/testsuite.sh new file mode 100755 index 000000000..c240d1184 --- /dev/null +++ b/testsuite/synth/oper02/testsuite.sh @@ -0,0 +1,10 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +for t in min01 max01; do + synth_tb $t +done + +echo "Test successful" |