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author | Tristan Gingold <tgingold@free.fr> | 2017-09-13 05:44:04 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2017-09-13 05:44:04 +0200 |
commit | bc0ade3887edc8aab6142f85f5d64a8e0fadfac6 (patch) | |
tree | b08d815ab7588d556f9a8220bc5b6bc3671f8deb | |
parent | 55c7ed6ce973af64e0d79fcd1e98a74647814980 (diff) | |
download | ghdl-bc0ade3887edc8aab6142f85f5d64a8e0fadfac6.tar.gz ghdl-bc0ade3887edc8aab6142f85f5d64a8e0fadfac6.tar.bz2 ghdl-bc0ade3887edc8aab6142f85f5d64a8e0fadfac6.zip |
ghdl_simul: also renames conversion.
-rw-r--r-- | src/vhdl/simulate/elaboration.adb | 8 | ||||
-rw-r--r-- | src/vhdl/simulate/execution.adb | 6 | ||||
-rw-r--r-- | src/vhdl/simulate/simulation-main.adb | 22 |
3 files changed, 27 insertions, 9 deletions
diff --git a/src/vhdl/simulate/elaboration.adb b/src/vhdl/simulate/elaboration.adb index 5904bd534..08872c833 100644 --- a/src/vhdl/simulate/elaboration.adb +++ b/src/vhdl/simulate/elaboration.adb @@ -1276,8 +1276,8 @@ package body Elaboration is Inter := Get_Association_Interface (Assoc, Port); case Get_Kind (Assoc) is when Iir_Kind_Association_Element_By_Expression => - if Get_In_Conversion (Assoc) = Null_Iir - and then Get_Out_Conversion (Assoc) = Null_Iir + if Get_Actual_Conversion (Assoc) = Null_Iir + and then Get_Formal_Conversion (Assoc) = Null_Iir then Actual := Get_Actual (Assoc); Formal := Get_Formal (Assoc); @@ -1311,8 +1311,8 @@ package body Elaboration is if Get_Whole_Association_Flag (Assoc) and then Get_Collapse_Signal_Flag (Assoc) then - pragma Assert (Get_In_Conversion (Assoc) = Null_Iir); - pragma Assert (Get_Out_Conversion (Assoc) = Null_Iir); + pragma Assert (Get_Actual_Conversion (Assoc) = Null_Iir); + pragma Assert (Get_Formal_Conversion (Assoc) = Null_Iir); pragma Assert (Is_Signal_Name (Get_Actual (Assoc))); declare Slot : constant Object_Slot_Type := diff --git a/src/vhdl/simulate/execution.adb b/src/vhdl/simulate/execution.adb index a10b18a13..18f42a7bd 100644 --- a/src/vhdl/simulate/execution.adb +++ b/src/vhdl/simulate/execution.adb @@ -3558,7 +3558,7 @@ package body Execution is end if; if Mode = Iir_Out_Mode then - if Get_Out_Conversion (Assoc) /= Null_Iir then + if Get_Formal_Conversion (Assoc) /= Null_Iir then -- For an OUT variable using an out conversion, don't -- associate with the actual, create a temporary value. Val := Create_Value_For_Type @@ -3574,7 +3574,7 @@ package body Execution is if Get_Kind (Assoc) = Iir_Kind_Association_Element_By_Expression then - Conv := Get_In_Conversion (Assoc); + Conv := Get_Actual_Conversion (Assoc); if Conv /= Null_Iir then Val := Execute_Assoc_Conversion (Subprg_Block, Conv, Val); @@ -3660,7 +3660,7 @@ package body Execution is -- Extract for individual association. Execute_Name_With_Base (Instance, Formal, Base, Val, Is_Sig); - Conv := Get_Out_Conversion (Assoc); + Conv := Get_Formal_Conversion (Assoc); if Conv /= Null_Iir then Val := Execute_Assoc_Conversion (Instance, Conv, Val); diff --git a/src/vhdl/simulate/simulation-main.adb b/src/vhdl/simulate/simulation-main.adb index 1b7f1eb63..3466c9d43 100644 --- a/src/vhdl/simulate/simulation-main.adb +++ b/src/vhdl/simulate/simulation-main.adb @@ -1,3 +1,21 @@ +-- Interpreted simulation +-- Copyright (C) 2014-2017 Tristan Gingold +-- +-- GHDL is free software; you can redistribute it and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation; either version 2, or (at your option) any later +-- version. +-- +-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY +-- WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with GHDL; see the file COPYING. If not, write to the Free +-- Software Foundation, 59 Temple Place - Suite 330, Boston, MA +-- 02111-1307, USA. + with Ada.Unchecked_Conversion; with Ada.Text_IO; use Ada.Text_IO; with Types; use Types; @@ -699,7 +717,7 @@ package body Simulation.Main is | Iir_Linkage_Mode => -- FORMAL_EXPR is a source for LOCAL_EXPR. declare - Out_Conv : constant Iir := Get_Out_Conversion (Assoc); + Out_Conv : constant Iir := Get_Formal_Conversion (Assoc); Src : Iir_Value_Literal_Acc; begin if Out_Conv /= Null_Iir then @@ -732,7 +750,7 @@ package body Simulation.Main is | Iir_Buffer_Mode | Iir_Linkage_Mode => declare - In_Conv : constant Iir := Get_In_Conversion (Assoc); + In_Conv : constant Iir := Get_Actual_Conversion (Assoc); Src : Iir_Value_Literal_Acc; begin if In_Conv /= Null_Iir then |