testsuite/synth: add test for #1250

3 files changed, 55 insertions, 0 deletions

diff --git a/testsuite/synth/issue1250/tb_theunit.vhdl b/testsuite/synth/issue1250/tb_theunit.vhdl
new file mode 100644
index 000000000..d3defd621
--- /dev/null
+++ b/testsuite/synth/issue1250/tb_theunit.vhdl
@@ -0,0 +1,20 @@
+entity tb_theunit is
+end tb_theunit;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_theunit is
+  signal d : std_logic;
+begin
+  dut: entity work.theunit
+    port map (d);
+
+  process
+  begin
+    wait for 1 ns;
+    assert d = '1' severity failure;
+    
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1250/testsuite.sh b/testsuite/synth/issue1250/testsuite.sh
new file mode 100755
index 000000000..cae69f6f6
--- /dev/null
+++ b/testsuite/synth/issue1250/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_tb theunit
+
+echo "Test successful"
diff --git a/testsuite/synth/issue1250/theunit.vhdl b/testsuite/synth/issue1250/theunit.vhdl
new file mode 100644
index 000000000..177c57507
--- /dev/null
+++ b/testsuite/synth/issue1250/theunit.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+entity theunit is
+  port (dout : out std_ulogic);
+end;
+
+architecture rtl of theunit is
+  subtype thenum_t is integer range 0 to 1;
+  type rec_t is record
+    -- NOTE: changing order of these members prevents crash
+    data0 : std_ulogic;
+    bankm : std_ulogic_vector(thenum_t);
+  end record;
+  signal r : rec_t;
+begin
+  thecomb : process(r)
+    variable v      : rec_t;
+    variable thenum : thenum_t := 1;
+  begin
+    v.data0 := '1';
+    v.bankm := (others => '1');
+    -- NOTE: removing any of the lines below prevents crash
+    v.bankm(thenum) := '0';
+    r <= v;
+    dout <= r.data0;
+  end process;
+end;
+