Rename overloaded Load_File and export it to python.

7 files changed, 16 insertions, 13 deletions

diff --git a/src/ghdldrv/ghdlcomp.adb b/src/ghdldrv/ghdlcomp.adb
index 5ccb1f9ab..6533d9225 100644
--- a/src/ghdldrv/ghdlcomp.adb
+++ b/src/ghdldrv/ghdlcomp.adb
@@ -215,7 +215,7 @@ package body Ghdlcomp is
       Design : Iir;
       Next_Design : Iir;
    begin
-      Res := Load_File (Name_Table.Get_Identifier (File));
+      Res := Load_File_Name (Name_Table.Get_Identifier (File));
       if Errorout.Nbr_Errors > 0 then
          raise Compilation_Error;
       end if;
@@ -239,7 +239,7 @@ package body Ghdlcomp is
       Unit : Iir;
       Next_Unit : Iir;
    begin
-      Design_File := Load_File (Id);
+      Design_File := Load_File_Name (Id);
       if Design_File = Null_Iir or else Errorout.Nbr_Errors > 0 then
          --  Stop now in case of error (file not found or parse error).
          return Design_File;
@@ -397,7 +397,7 @@ package body Ghdlcomp is
       --  Parse all files.
       for I in Args'Range loop
          Id := Name_Table.Get_Identifier (Args (I).all);
-         Design_File := Load_File (Id);
+         Design_File := Load_File_Name (Id);
          if Errorout.Nbr_Errors > 0 then
             raise Compilation_Error;
          end if;
diff --git a/src/ghdldrv/ghdllocal.adb b/src/ghdldrv/ghdllocal.adb
index 568872ab3..9df81a7b2 100644
--- a/src/ghdldrv/ghdllocal.adb
+++ b/src/ghdldrv/ghdllocal.adb
@@ -639,7 +639,7 @@ package body Ghdllocal is
 
       for I in Args'Range loop
          Id := Get_Identifier (Args (I).all);
-         Design_File := Sem_Lib.Load_File (Id);
+         Design_File := Sem_Lib.Load_File_Name (Id);
          if Design_File /= Null_Iir then
             Unit := Get_First_Design_Unit (Design_File);
             while Unit /= Null_Iir loop
@@ -700,7 +700,7 @@ package body Ghdllocal is
       --  Parse all files.
       for I in Args'Range loop
          Id := Name_Table.Get_Identifier (Args (I).all);
-         Design_File := Sem_Lib.Load_File (Id);
+         Design_File := Sem_Lib.Load_File_Name (Id);
          if Design_File /= Null_Iir then
             Unit := Get_First_Design_Unit (Design_File);
             while Unit /= Null_Iir loop
@@ -787,7 +787,7 @@ package body Ghdllocal is
          Put (File_Name);
          Put_Line (":");
       end if;
-      Design_File := Sem_Lib.Load_File (Id);
+      Design_File := Sem_Lib.Load_File_Name (Id);
       if Design_File = Null_Iir then
          raise Errorout.Compilation_Error;
       end if;
diff --git a/src/ghdldrv/ghdlprint.adb b/src/ghdldrv/ghdlprint.adb
index 8470b6ea3..4d367621c 100644
--- a/src/ghdldrv/ghdlprint.adb
+++ b/src/ghdldrv/ghdlprint.adb
@@ -680,7 +680,7 @@ package body Ghdlprint is
       --  exist.
       for I in Args'Range loop
          Id := Get_Identifier (Args (I).all);
-         Design_File := Load_File (Id);
+         Design_File := Load_File_Name (Id);
          if Design_File = Null_Iir then
             raise Compile_Error;
          end if;
@@ -994,7 +994,7 @@ package body Ghdlprint is
       --  Parse all files.
       for I in Args'Range loop
          Id := Name_Table.Get_Identifier (Args (I).all);
-         Design_File := Load_File (Id);
+         Design_File := Load_File_Name (Id);
          if Design_File = Null_Iir then
             raise Errorout.Compilation_Error;
          end if;
diff --git a/src/vhdl/python/libghdl/thin.py b/src/vhdl/python/libghdl/thin.py
index 43ed6ce2f..4de91833d 100644
--- a/src/vhdl/python/libghdl/thin.py
+++ b/src/vhdl/python/libghdl/thin.py
@@ -200,6 +200,9 @@ class Canon:
     Extract_Sequential_Statement_Chain_Sensitivity = \
         libghdl.canon__canon_extract_sequential_statement_chain_sensitivity
 
+class Sem_Lib:
+    Load_File = libghdl.sem_lib__load_file
+
 
 # std.standard
 
diff --git a/src/vhdl/sem_lib.adb b/src/vhdl/sem_lib.adb
index d47bf70e0..6139d245e 100644
--- a/src/vhdl/sem_lib.adb
+++ b/src/vhdl/sem_lib.adb
@@ -61,7 +61,7 @@ package body Sem_Lib is
    -- parse a file.
    -- Return a design_file without putting it into the library
    -- (because it was not analyzed).
-   function Load_File (File_Name: Name_Id) return Iir_Design_File
+   function Load_File_Name (File_Name: Name_Id) return Iir_Design_File
    is
       Fe : Source_File_Entry;
    begin
@@ -71,7 +71,7 @@ package body Sem_Lib is
          return Null_Iir;
       end if;
       return Load_File (Fe);
-   end Load_File;
+   end Load_File_Name;
 
    procedure Finish_Compilation
      (Unit : Iir_Design_Unit; Main : Boolean := False)
diff --git a/src/vhdl/sem_lib.ads b/src/vhdl/sem_lib.ads
index 4d18356ae..7f57833b5 100644
--- a/src/vhdl/sem_lib.ads
+++ b/src/vhdl/sem_lib.ads
@@ -24,7 +24,7 @@ package Sem_Lib is
    --    absolute path).
    --  Emit an error if the file cannot be opened.
    --  Return NULL_IIR in case of parse error.
-   function Load_File (File_Name: Name_Id) return Iir_Design_File;
+   function Load_File_Name (File_Name: Name_Id) return Iir_Design_File;
    function Load_File (File : Source_File_Entry) return Iir_Design_File;
 
    --  Load, parse, analyze, back-end a design_unit if necessary.
diff --git a/src/vhdl/translate/ortho_front.adb b/src/vhdl/translate/ortho_front.adb
index 1eb8a3cd8..f17713b0f 100644
--- a/src/vhdl/translate/ortho_front.adb
+++ b/src/vhdl/translate/ortho_front.adb
@@ -273,7 +273,7 @@ package body Ortho_Front is
       Flags.Flag_Elaborate := False;
 
       --  Read and parse the file.
-      Res := Load_File (Vhdl_File);
+      Res := Load_File_Name (Vhdl_File);
       if Errorout.Nbr_Errors > 0 then
          raise Compilation_Error;
       end if;
@@ -454,7 +454,7 @@ package body Ortho_Front is
                begin
                   L := Anaelab_Files;
                   while L /= null loop
-                     Res := Load_File (L.Id);
+                     Res := Load_File_Name (L.Id);
                      if Errorout.Nbr_Errors > 0 then
                         raise Compilation_Error;
                      end if;