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| author | Tristan Gingold <tgingold@free.fr> | 2022-06-28 02:42:34 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-06-28 02:42:34 +0200 |
| commit | b722e6e03801eaed1d8f64ad70119658c3898ec2 (patch) | |
| tree | 00b08984c97657fd3d5ef5ae54459803ba3e68c9 | |
| parent | 7e89ed2b5108163d52788927fe49b0c5686adbd6 (diff) | |
| download | ghdl-b722e6e03801eaed1d8f64ad70119658c3898ec2.tar.gz ghdl-b722e6e03801eaed1d8f64ad70119658c3898ec2.tar.bz2 ghdl-b722e6e03801eaed1d8f64ad70119658c3898ec2.zip | |
testsuite/synth: strenghten test #2113
| -rwxr-xr-x | testsuite/synth/issue2113/testsuite.sh | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/testsuite/synth/issue2113/testsuite.sh b/testsuite/synth/issue2113/testsuite.sh index b2f61e07e..9ab046cc4 100755 --- a/testsuite/synth/issue2113/testsuite.sh +++ b/testsuite/synth/issue2113/testsuite.sh @@ -8,5 +8,8 @@ synth --out=verilog -Wno-nowrite a.vhdl -e > syn_a.v if grep channel syn_a.v; then exit 1 fi +if grep "0'" syn_a.v; then + exit 1; +fi echo "Test successful" |