testsuite/synth: add tests for previous commit.

3 files changed, 64 insertions, 0 deletions

diff --git a/testsuite/synth/bug02/repro1.vhdl b/testsuite/synth/bug02/repro1.vhdl
new file mode 100644
index 000000000..f138f17dc
--- /dev/null
+++ b/testsuite/synth/bug02/repro1.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro1 is
+  port (clk : std_logic;
+        o1 : out std_logic;
+        o2 : out std_logic);
+end repro1;
+
+architecture behav of repro1 is
+  signal v : natural range 0 to 0;
+begin
+  process (clk)
+  begin
+    if rising_edge(clk) then
+      o1 <= '1';
+      v <= 0;
+    end if;
+  end process;
+
+  o2 <= '1' when v = 0 else '0';
+end behav;
diff --git a/testsuite/synth/bug02/repro2.vhdl b/testsuite/synth/bug02/repro2.vhdl
new file mode 100644
index 000000000..6968e254d
--- /dev/null
+++ b/testsuite/synth/bug02/repro2.vhdl
@@ -0,0 +1,29 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro2 is
+  port (
+    clk_i          : in  std_logic;
+    rst_n_i        : in  std_logic;
+    vec_i         : in  std_logic_vector(0 to 0)
+  );
+end repro2;
+
+architecture rtl of repro2 is
+  signal s_sel : natural range vec_i'range;
+  signal s_true : std_logic;
+begin
+  s_true <= '1';
+
+  process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+        for i in vec_i'range loop
+          if s_true = '1' then
+            s_sel <= i;
+            exit;
+          end if;
+        end loop;
+    end if;
+  end process;
+end rtl;
diff --git a/testsuite/synth/bug02/testsuite.sh b/testsuite/synth/bug02/testsuite.sh
new file mode 100755
index 000000000..2a65485e4
--- /dev/null
+++ b/testsuite/synth/bug02/testsuite.sh
@@ -0,0 +1,13 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+#GHDL_STD_FLAGS=--std=08
+for t in repro1 repro2; do
+  synth $t.vhdl -e $t > syn_$t.vhdl
+  analyze syn_$t.vhdl
+done
+
+clean
+
+echo "Test successful"