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| author | Tristan Gingold <tgingold@free.fr> | 2021-03-17 20:16:24 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-03-17 20:16:24 +0100 |
| commit | b38003fe6a2a12af7f2e13b4ac8c28245a48575e (patch) | |
| tree | f147ddd5dce3aba042dde4099439b2e27be2764e | |
| parent | 4be07f298050ec2de183be699ad7e9650b5b5b9c (diff) | |
| download | ghdl-b38003fe6a2a12af7f2e13b4ac8c28245a48575e.tar.gz ghdl-b38003fe6a2a12af7f2e13b4ac8c28245a48575e.tar.bz2 ghdl-b38003fe6a2a12af7f2e13b4ac8c28245a48575e.zip | |
synth: handle loc attribute (for ports). Fix #1682
| -rw-r--r-- | src/synth/synth-decls.adb | 3 | ||||
| -rw-r--r-- | src/synth/synth-stmts.adb | 3 |
2 files changed, 5 insertions, 1 deletions
diff --git a/src/synth/synth-decls.adb b/src/synth/synth-decls.adb index d3a903b00..1539b0039 100644 --- a/src/synth/synth-decls.adb +++ b/src/synth/synth-decls.adb @@ -612,7 +612,8 @@ package body Synth.Decls is case Get_Kind (Obj) is when Iir_Kind_Signal_Declaration - | Iir_Kind_Variable_Declaration => + | Iir_Kind_Variable_Declaration + | Iir_Kind_Interface_Signal_Declaration => V := Get_Value (Syn_Inst, Obj); pragma Assert (V.Val.Kind = Value_Wire); Inst := Get_Net_Parent (Get_Wire_Gate (V.Val.W)); diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb index a19ca987a..8ec6fdf33 100644 --- a/src/synth/synth-stmts.adb +++ b/src/synth/synth-stmts.adb @@ -3700,6 +3700,9 @@ package body Synth.Stmts is Synth_Attribute_Formal (Syn_Inst, Val, Id_Anyconst); when Name_Anyseq => Synth_Attribute_Formal (Syn_Inst, Val, Id_Anyseq); + when Name_Loc => + -- Applies to nets/ports. + null; when others => Warning_Msg_Synth (+Spec, "unhandled attribute %i", (1 => +Id)); end case; |