testsuite/gna: add a reproducer for #1588

3 files changed, 225 insertions, 0 deletions

diff --git a/testsuite/gna/issue1588/libs12.vhdl b/testsuite/gna/issue1588/libs12.vhdl
new file mode 100644
index 000000000..5dd9967a7
--- /dev/null
+++ b/testsuite/gna/issue1588/libs12.vhdl
@@ -0,0 +1,79 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use work.all;
+
+entity libs12 is
+end entity;
+
+architecture tb of libs12 is
+
+  component tent
+    port(
+      rst_n : in std_logic;
+      clk   : in std_logic;
+      period : in integer;
+      clk_o : out std_logic;
+      op1 : out integer;
+      op2 : out integer
+      );
+  end component;
+
+  signal tclk : std_logic := '0';
+  signal trst : std_logic := '0';
+  signal tper : integer := 1;
+  signal oclk : std_logic;
+  signal oop1 : integer;
+  signal oop2 : integer;
+  signal oclk1 : std_logic;
+  signal oop11 : integer;
+  signal oop21 : integer;
+  
+begin
+
+  process
+    variable v_cnt : integer := 0;
+  begin
+    trst  <= '0';
+    wait for 1 ns;
+    trst  <= '1';
+    wait for 1 ns;
+    while v_cnt < 50 loop
+      --report "clk";
+      tclk <= not tclk;
+      wait for 1 ns;
+      v_cnt := v_cnt + 1;
+    end loop;
+  end process;
+
+
+u1: entity tent(rtl)
+  port map(
+    rst_n  => trst,
+    clk    => tclk,
+    period => tper,
+    clk_o  => oclk,
+    op1    => oop1,
+    op2    => oop2
+    );
+
+u2: entity tent(bhv)
+  port map(
+    rst_n  => trst,
+    clk    => tclk,
+    period => tper,
+    clk_o  => oclk1,
+    op1    => oop11,
+    op2    => oop21
+    );
+
+  mon: process(oclk)
+  begin
+    if oclk'event and oclk = '1' then
+      report "Rising edge oclk with oop1: " & integer'image(oop1) &
+      " and oop2: " & integer'image(oop2);
+      report "Rising edge oclk with oop11: " & integer'image(oop11) &
+      " and oop12: " & integer'image(oop21);
+    end if;
+  end process mon;
+
+end tb;
diff --git a/testsuite/gna/issue1588/tent.vhdl b/testsuite/gna/issue1588/tent.vhdl
new file mode 100644
index 000000000..12cead8a4
--- /dev/null
+++ b/testsuite/gna/issue1588/tent.vhdl
@@ -0,0 +1,136 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity tent is
+  port(
+    rst_n : in std_logic;
+    clk   : in std_logic;
+    period : in integer;
+    clk_o : out std_logic;
+    op1 : out integer;
+    op2 : out integer
+    );
+    
+begin
+
+  clk_mon: process(clk)
+    variable tl : time := 0 ns;
+    variable td : time;
+    variable lp : time;
+  begin
+    if(clk'event) then
+      --report "" & time'image(now);
+      if clk = '1' then
+        td := now - tl;
+        tl := now;
+        if lp /= td then
+          report "clk period is: " & time'image(td);
+          lp := td;
+        end if;
+      end if;
+      
+    end if;
+  end process;
+  
+end entity tent;
+
+architecture rtl of tent is
+
+  signal bv : bit_vector(15 downto 0) := (others => '1');
+  signal stdv : std_logic_vector(15 downto 0);
+  signal clk1  : std_logic := '1';
+  
+  signal cnt : integer := 0;
+  signal cnt1 : integer := 0;
+  
+  signal operiod : time;
+  
+begin
+
+  --operiod <= period * 1 ns;
+
+  clock : process(clk)
+    variable clk_v : std_logic := '0';
+  begin
+    if clk'event and clk = '1' then
+      clk_v := not clk_v;
+      clk_o <= clk_v;
+    end if;
+    if cnt > 20 then
+      report "END  SIM ..." severity failure;
+    end if;
+  end process clock;
+
+  process(clk)
+  begin
+    if clk'event and clk = '1' then
+      cnt <= cnt + 1;
+      --report "clk event ...";
+      op1 <= cnt;
+      clk1 <= not clk1;
+    end if;
+  end process;
+
+  process(clk1)
+  begin
+    if(clk1'event and clk1 = '1') then
+      cnt1 <= 2 ** cnt;
+      --report "clk1 event ...";
+      op2 <= cnt1;
+    end if;
+  end process;
+
+end rtl;
+
+
+architecture bhv of tent is
+
+  signal bv : bit_vector(15 downto 0) := (others => '1');
+  signal stdv : std_logic_vector(15 downto 0);
+  signal clk1  : std_logic := '1';
+  
+  signal cnt : integer := 0;
+  signal cnt1 : integer := 0;
+  
+  signal operiod : time;
+  
+begin
+
+  process
+  begin
+    report "BHV ...";
+    wait;
+  end process;
+
+  clock : process(clk)
+    variable clk_v : std_logic := '0';
+  begin
+    if clk'event and clk = '1' then
+      clk_v := not clk_v;
+      clk_o <= clk_v;
+    end if;
+    if cnt > 20 then
+      report "END  SIM ..." severity failure;
+    end if;
+  end process clock;
+
+  process(clk)
+  begin
+    if clk'event and clk = '1' then
+      cnt <= cnt + 1;
+      --report "clk event ...";
+      op1 <= cnt;
+      clk1 <= not clk1;
+    end if;
+  end process;
+
+  process(clk1)
+  begin
+    if(clk1'event and clk1 = '1') then
+      cnt1 <= 2 ** cnt;
+      --report "clk1 event ...";
+      op2 <= cnt1;
+    end if;
+  end process;
+
+end bhv;
diff --git a/testsuite/gna/issue1588/testsuite.sh b/testsuite/gna/issue1588/testsuite.sh
new file mode 100755
index 000000000..a5bcc63d7
--- /dev/null
+++ b/testsuite/gna/issue1588/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze tent.vhdl
+analyze_failure libs12.vhdl
+
+clean
+
+echo "Test successful"