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authorTristan Gingold <tgingold@free.fr>2020-04-06 19:07:37 +0200
committerTristan Gingold <tgingold@free.fr>2020-04-06 20:11:00 +0200
commita3ebbb09a4212dee24beb7a437d89610e4c170b7 (patch)
tree6245211fb10f0850e1fba34af8b44cc1619f2576
parentea7b6490368a4fceb370cc8bc7069133a3217285 (diff)
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testsuite/synth: add a test for #1199
-rw-r--r--testsuite/synth/issue1199/issue1.vhdl15
-rw-r--r--testsuite/synth/issue1199/issue2.vhdl14
-rwxr-xr-xtestsuite/synth/issue1199/testsuite.sh8
3 files changed, 37 insertions, 0 deletions
diff --git a/testsuite/synth/issue1199/issue1.vhdl b/testsuite/synth/issue1199/issue1.vhdl
new file mode 100644
index 000000000..6a521008c
--- /dev/null
+++ b/testsuite/synth/issue1199/issue1.vhdl
@@ -0,0 +1,15 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity issue1 is
+ port(
+ a : in std_logic_vector(7 downto 0);
+ b : out std_logic_vector(2 downto 0)
+ );
+end issue1;
+
+architecture behavior of issue1 is
+begin
+ b <= std_logic_vector(unsigned(a) + 1);
+end behavior;
diff --git a/testsuite/synth/issue1199/issue2.vhdl b/testsuite/synth/issue1199/issue2.vhdl
new file mode 100644
index 000000000..888b074d2
--- /dev/null
+++ b/testsuite/synth/issue1199/issue2.vhdl
@@ -0,0 +1,14 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity issue2 is
+ port(
+ a : in std_logic_vector(7 downto 0);
+ b : out std_logic_vector(2 downto 0)
+ );
+end issue2;
+
+architecture behavior of issue2 is
+begin
+ b <= a;
+end behavior;
diff --git a/testsuite/synth/issue1199/testsuite.sh b/testsuite/synth/issue1199/testsuite.sh
new file mode 100755
index 000000000..92319c2d9
--- /dev/null
+++ b/testsuite/synth/issue1199/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_failure issue1.vhdl -e
+synth_failure issue2.vhdl -e
+
+echo "Test successful"