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author | Tristan Gingold <tgingold@free.fr> | 2022-04-13 21:25:14 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-04-13 21:25:14 +0200 |
commit | a2677c042c4594357c23ac2f1c9e09b1b5bf0e41 (patch) | |
tree | adfade0f7e42dc1b59a22bebac9813cce393d371 | |
parent | 52cecb9c6e7efb0bd20ef30e4aba564d1e205011 (diff) | |
download | ghdl-a2677c042c4594357c23ac2f1c9e09b1b5bf0e41.tar.gz ghdl-a2677c042c4594357c23ac2f1c9e09b1b5bf0e41.tar.bz2 ghdl-a2677c042c4594357c23ac2f1c9e09b1b5bf0e41.zip |
testsuite/synth: add a test for #2035
-rw-r--r-- | testsuite/synth/issue2035/cdc_fifo_rtl.vhdl | 13 | ||||
-rwxr-xr-x | testsuite/synth/issue2035/testsuite.sh | 8 |
2 files changed, 21 insertions, 0 deletions
diff --git a/testsuite/synth/issue2035/cdc_fifo_rtl.vhdl b/testsuite/synth/issue2035/cdc_fifo_rtl.vhdl new file mode 100644 index 000000000..059804d69 --- /dev/null +++ b/testsuite/synth/issue2035/cdc_fifo_rtl.vhdl @@ -0,0 +1,13 @@ + +ENTITY cdc_fifo IS +END ENTITY cdc_fifo; + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ARCHITECTURE rtl OF cdc_fifo IS + SIGNAL ver_clk : std_logic; + ATTRIBUTE gclk : boolean; + ATTRIBUTE gclk OF ver_clk : SIGNAL is true; +BEGIN +END ARCHITECTURE; diff --git a/testsuite/synth/issue2035/testsuite.sh b/testsuite/synth/issue2035/testsuite.sh new file mode 100755 index 000000000..f1064aaca --- /dev/null +++ b/testsuite/synth/issue2035/testsuite.sh @@ -0,0 +1,8 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +synth -Werror cdc_fifo_rtl.vhdl -e > syn_cdc_fifo_rtl.vhdl + +echo "Test successful" |