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| author | Tristan Gingold <tgingold@free.fr> | 2019-09-30 20:58:09 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-09-30 20:58:09 +0200 |
| commit | 9aeab4488aef1a576d648ce2a14d3bc3a893f1e6 (patch) | |
| tree | c8a871b6a44452b47bf4aecb88e3e328e1a9e595 | |
| parent | fce1061ee2be3198b7fe323f15092f473ae53919 (diff) | |
| download | ghdl-9aeab4488aef1a576d648ce2a14d3bc3a893f1e6.tar.gz ghdl-9aeab4488aef1a576d648ce2a14d3bc3a893f1e6.tar.bz2 ghdl-9aeab4488aef1a576d648ce2a14d3bc3a893f1e6.zip | |
synth: improve support of * and /. Fix #953
| -rw-r--r-- | src/synth/netlists-builders.adb | 6 | ||||
| -rw-r--r-- | src/synth/netlists-gates.ads | 6 | ||||
| -rw-r--r-- | src/synth/synth-oper.adb | 36 |
3 files changed, 46 insertions, 2 deletions
diff --git a/src/synth/netlists-builders.adb b/src/synth/netlists-builders.adb index fb54805eb..b6fdcbb92 100644 --- a/src/synth/netlists-builders.adb +++ b/src/synth/netlists-builders.adb @@ -417,10 +417,16 @@ package body Netlists.Builders is Get_Identifier ("add"), Id_Add); Create_Dyadic_Module (Design, Res.M_Dyadic (Id_Sub), Get_Identifier ("sub"), Id_Sub); + Create_Dyadic_Module (Design, Res.M_Dyadic (Id_Umul), Get_Identifier ("umul"), Id_Umul); Create_Dyadic_Module (Design, Res.M_Dyadic (Id_Smul), Get_Identifier ("smul"), Id_Smul); + Create_Dyadic_Module (Design, Res.M_Dyadic (Id_Udiv), + Get_Identifier ("udiv"), Id_Udiv); + Create_Dyadic_Module (Design, Res.M_Dyadic (Id_Sdiv), + Get_Identifier ("sdiv"), Id_Sdiv); + Create_Dyadic_Module (Design, Res.M_Dyadic (Id_Umod), Get_Identifier ("umod"), Id_Umod); Create_Dyadic_Module (Design, Res.M_Dyadic (Id_Smod), diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads index 44afec700..f45313e10 100644 --- a/src/synth/netlists-gates.ads +++ b/src/synth/netlists-gates.ads @@ -35,8 +35,10 @@ package Netlists.Gates is Id_Sub : constant Module_Id := 10; Id_Umul : constant Module_Id := 11; Id_Smul : constant Module_Id := 12; - Id_Umod : constant Module_Id := 13; - Id_Smod : constant Module_Id := 14; + Id_Udiv : constant Module_Id := 13; + Id_Sdiv : constant Module_Id := 14; + Id_Umod : constant Module_Id := 15; + Id_Smod : constant Module_Id := 16; subtype Dyadic_Module_Id is Module_Id range Id_And .. Id_Smod; diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index ddb4b2e88..096bbba44 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -476,6 +476,42 @@ package body Synth.Oper is Set_Location (N, Expr); return Create_Value_Net (N, Rtype); end; + when Iir_Predefined_Ieee_Numeric_Std_Mul_Uns_Nat => + declare + L : constant Net := Get_Net (Left); + R : constant Net := Get_Net (Right); + Lw : constant Width := Get_Width (L); + W : constant Width := 2 * Lw; + L1, R1 : Net; + Rtype : Type_Acc; + N : Net; + begin + L1 := Synth_Uresize (L, W, Expr); + R1 := Synth_Uresize (R, W, Expr); + Rtype := Create_Vec_Type_By_Length (W, Left.Typ.Vec_El); + N := Build_Dyadic (Build_Context, Id_Umul, L1, R1); + Set_Location (N, Expr); + return Create_Value_Net (N, Rtype); + end; + + when Iir_Predefined_Ieee_Numeric_Std_Div_Uns_Nat => + declare + L : constant Net := Get_Net (Left); + R : constant Net := Get_Net (Right); + Lw : constant Width := Get_Width (L); + W : constant Width := Width'Max (Lw, Get_Width (R)); + L1, R1 : Net; + Rtype : Type_Acc; + N : Net; + begin + L1 := Synth_Uresize (L, W, Expr); + R1 := Synth_Uresize (R, W, Expr); + Rtype := Create_Vec_Type_By_Length (Lw, Left.Typ.Vec_El); + N := Build_Dyadic (Build_Context, Id_Udiv, L1, R1); + Set_Location (N, Expr); + N := Synth_Uresize (N, Lw, Expr); + return Create_Value_Net (N, Rtype); + end; when Iir_Predefined_Ieee_Numeric_Std_Eq_Uns_Nat => -- "=" (Unsigned, Natural) |