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| author | Tristan Gingold <tgingold@free.fr> | 2021-03-18 18:39:22 +0100 | 
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-03-18 18:39:22 +0100 | 
| commit | 9a80de30f485c9af8aaeb9eeb9ec986c7fffa6f8 (patch) | |
| tree | 775c6e3fdb50e19a714e34a72f64bcd7c6302d6f | |
| parent | c4256d931efe445aab9153486c9e5082d23056eb (diff) | |
| download | ghdl-9a80de30f485c9af8aaeb9eeb9ec986c7fffa6f8.tar.gz ghdl-9a80de30f485c9af8aaeb9eeb9ec986c7fffa6f8.tar.bz2 ghdl-9a80de30f485c9af8aaeb9eeb9ec986c7fffa6f8.zip | |
testsuite/gna: add test for #1687
| -rw-r--r-- | testsuite/gna/issue1687/ent.vhdl | 16 | ||||
| -rw-r--r-- | testsuite/gna/issue1687/pkg.vhdl | 17 | ||||
| -rwxr-xr-x | testsuite/gna/issue1687/testsuite.sh | 10 | 
3 files changed, 43 insertions, 0 deletions
| diff --git a/testsuite/gna/issue1687/ent.vhdl b/testsuite/gna/issue1687/ent.vhdl new file mode 100644 index 000000000..1ccfdde1e --- /dev/null +++ b/testsuite/gna/issue1687/ent.vhdl @@ -0,0 +1,16 @@ +use work.pack_RC_Add_n_F.all; + +entity RC_Add_n_F is +    generic(n : natural := 4); +    port(A, B : in bit_vector(n-1 downto 0); Cin: in bit; Sum: out bit_vector(n-1 downto 0); Cout: out bit); +end RC_Add_n_F; + +architecture Arch_RC_Add_n_F of RC_Add_n_F is +    signal result: bit_vector(n downto 0); +begin +    -- result <= RC_Add_n(A(3 downto 0), B, Cin);                               -- Works +    -- result <= RC_Add_n(A => A(3 downto 0), B => B, Cin => Cin);              -- Works +    result <= RC_Add_n(A(3 downto 0) => A(3 downto 0), B => B, Cin => Cin);     -- Fails +    Sum <= result(n-1 downto 0); +    Cout <= result(n); +end Arch_RC_Add_n_F; diff --git a/testsuite/gna/issue1687/pkg.vhdl b/testsuite/gna/issue1687/pkg.vhdl new file mode 100644 index 000000000..0e2b87c00 --- /dev/null +++ b/testsuite/gna/issue1687/pkg.vhdl @@ -0,0 +1,17 @@ +package pack_RC_Add_n_F is +    function RC_Add_n( A, B :bit_vector; Cin : bit) return bit_vector; +end pack_RC_Add_n_F; +     +package body pack_RC_Add_n_F is +    function RC_Add_n( A, B :bit_vector; Cin : bit) return bit_vector is +        variable C:bit := Cin; +        variable SUM:bit_vector(A'length downto 0); +    begin +        loop_add_m: for I in 0 to A'length-1 loop +            SUM(I) := (A(I) xor B(I)) xor C; +            C := (A(I) and B(I)) or (C and (A(I) xor B(I) )); +        end loop loop_add_m; +        SUM(A'length) := C; +        return SUM; +    end RC_Add_n; +end pack_RC_Add_n_F; diff --git a/testsuite/gna/issue1687/testsuite.sh b/testsuite/gna/issue1687/testsuite.sh new file mode 100755 index 000000000..0c596dd74 --- /dev/null +++ b/testsuite/gna/issue1687/testsuite.sh @@ -0,0 +1,10 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze pkg.vhdl ent.vhdl +elab_simulate_failure rc_add_n_f + +clean + +echo "Test successful" | 
