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| author | Tristan Gingold <tgingold@free.fr> | 2021-12-19 18:06:36 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-12-19 18:07:07 +0100 |
| commit | 99903b0932d000e92e2ed08d71c5354be0242093 (patch) | |
| tree | c442b8632932330c2e77273d7ca7bf31cc2be6e8 | |
| parent | c31919740777ff7f843d3f197586d15f16145a53 (diff) | |
| download | ghdl-99903b0932d000e92e2ed08d71c5354be0242093.tar.gz ghdl-99903b0932d000e92e2ed08d71c5354be0242093.tar.bz2 ghdl-99903b0932d000e92e2ed08d71c5354be0242093.zip | |
synth: add assertions
| -rw-r--r-- | src/synth/synth-vhdl_insts.adb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/synth/synth-vhdl_insts.adb b/src/synth/synth-vhdl_insts.adb index 235d9ed8e..b02d2df69 100644 --- a/src/synth/synth-vhdl_insts.adb +++ b/src/synth/synth-vhdl_insts.adb @@ -121,6 +121,8 @@ package body Synth.Vhdl_Insts is end if; Inter := Get_Generic_Chain (Params.Decl); while Inter /= Null_Node loop + pragma Assert (Get_Kind (Inter) + = Iir_Kind_Interface_Constant_Declaration); if not Is_Equal (Get_Value (Obj.Syn_Inst, Inter), Get_Value (Params.Syn_Inst, Inter)) then @@ -131,6 +133,8 @@ package body Synth.Vhdl_Insts is Inter := Get_Port_Chain (Params.Decl); while Inter /= Null_Node loop + pragma Assert (Get_Kind (Inter) + = Iir_Kind_Interface_Signal_Declaration); if not Is_Fully_Constrained_Type (Get_Type (Inter)) then if not Are_Types_Equal (Get_Value (Obj.Syn_Inst, Inter).Typ, Get_Value (Params.Syn_Inst, Inter).Typ) |