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authorTristan Gingold <tgingold@free.fr>2019-07-08 07:51:12 +0200
committerTristan Gingold <tgingold@free.fr>2019-07-08 18:27:03 +0200
commit9756bb517abcbeaa3156e1dcc18081ac0b651d8d (patch)
tree4daa4b831f8d55bf3e149d389ad3d84a19eb8460
parent19a81f348c8e80d97ab85439bca66749f66b399d (diff)
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vhdl simul-elaboration: minor rewrite.
-rw-r--r--src/vhdl/simulate/simul-elaboration.adb4
1 files changed, 1 insertions, 3 deletions
diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb
index fe89d48c7..b4f690ab4 100644
--- a/src/vhdl/simulate/simul-elaboration.adb
+++ b/src/vhdl/simulate/simul-elaboration.adb
@@ -1664,7 +1664,7 @@ package body Simul.Elaboration is
Arch : Iir;
Config : Iir;
begin
- case Get_Kind (Aspect) is
+ case Iir_Kinds_Entity_Aspect (Get_Kind (Aspect)) is
when Iir_Kind_Entity_Aspect_Entity =>
Arch := Get_Architecture (Aspect);
if Arch = Null_Iir then
@@ -1681,8 +1681,6 @@ package body Simul.Elaboration is
(Get_Block_Configuration (Config));
when Iir_Kind_Entity_Aspect_Open =>
return;
- when others =>
- raise Internal_Error;
end case;
Config := Get_Block_Configuration (Config);