vhdl-sem_assocs: relax constrained on type conversion of formal

Fix #2422

1 files changed, 19 insertions, 3 deletions

diff --git a/src/vhdl/vhdl-sem_assocs.adb b/src/vhdl/vhdl-sem_assocs.adb
index b36f05640..cfafd25c0 100644
--- a/src/vhdl/vhdl-sem_assocs.adb
+++ b/src/vhdl/vhdl-sem_assocs.adb
@@ -2275,15 +2275,31 @@ package body Vhdl.Sem_Assocs is
            and then not Is_Fully_Constrained_Type (Get_Type (In_Conv))
          then
             Error_Msg_Sem
-              (+Assoc, "type of actual conversion must be fully constrained");
+              (+Get_Type_Mark (In_Conv),
+               "type of actual conversion must be fully constrained");
          end if;
          if (Get_Mode (Inter) in Iir_Out_Modes
                or else Get_Mode (Inter) = Iir_Linkage_Mode)
            and then Out_Conv /= Null_Iir
            and then not Is_Fully_Constrained_Type (Get_Type (Out_Conv))
          then
-            Error_Msg_Sem
-              (+Assoc, "type of formal conversion must be fully constrained");
+            declare
+               Msgid : Msgid_Type;
+            begin
+               if Flag_Relaxed_Rules
+                 and then Get_Kind (Out_Conv) = Iir_Kind_Type_Conversion
+               then
+                  --  With -frelaxed, the bounds of the formal could be
+                  --  computed using an implicit type conversion from the
+                  --  actual bounds.
+                  Msgid := Warnid_Port;
+               else
+                  Msgid := Msgid_Error;
+               end if;
+               Report_Msg
+                 (Msgid, Semantic, +Get_Type_Mark (Out_Conv),
+                  "type of formal conversion must be fully constrained");
+            end;
          end if;
       end if;