synth-oper: Support Iir_Predefined_Enum_Greater{,_Equal}

5 files changed, 108 insertions, 0 deletions

diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb
index 4493db681..3a5c0edda 100644
--- a/src/synth/synth-oper.adb
+++ b/src/synth/synth-oper.adb
@@ -875,6 +875,10 @@ package body Synth.Oper is
             return Synth_Compare (Id_Ule, Boolean_Type);
          when Iir_Predefined_Enum_Less =>
             return Synth_Compare (Id_Ult, Boolean_Type);
+         when Iir_Predefined_Enum_Greater_Equal =>
+            return Synth_Compare (Id_Uge, Boolean_Type);
+         when Iir_Predefined_Enum_Greater =>
+            return Synth_Compare (Id_Ugt, Boolean_Type);
 
          when Iir_Predefined_Std_Ulogic_Match_Equality =>
             return Synth_Compare (Id_Eq, Logic_Type);
diff --git a/testsuite/synth/enum01/tb_test.vhdl b/testsuite/synth/enum01/tb_test.vhdl
new file mode 100644
index 000000000..9ecccee95
--- /dev/null
+++ b/testsuite/synth/enum01/tb_test.vhdl
@@ -0,0 +1,62 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.test_pkg.all;
+
+entity tb_test is
+end entity;
+
+architecture a of tb_test is
+	type reference_arr_t is array(number_t, number_t) of std_logic_vector(1 to 6);
+	signal reference_arr : reference_arr_t;
+
+	signal x, y : number_t;
+	signal eq, neq, lt, lte, gt, gte : boolean;
+	signal result : std_logic_vector(1 to 6);
+begin
+	reference_arr(ONE,   ONE)   <= "100101";
+	reference_arr(ONE,   TWO)   <= "011100";
+	reference_arr(ONE,   THREE) <= "011100";
+	reference_arr(TWO,   ONE)   <= "010011";
+	reference_arr(TWO,   TWO)   <= "100101";
+	reference_arr(TWO,   THREE) <= "011100";
+	reference_arr(THREE, ONE)   <= "010011";
+	reference_arr(THREE, TWO)   <= "010011";
+	reference_arr(THREE, THREE) <= "100101";
+
+	process
+	begin
+		for a in ONE to THREE loop
+			for b in ONE to THREE loop
+				x <= a;
+				y <= b;
+
+				wait for 10 ns;
+
+				assert result = reference_arr(a, b);
+			end loop;
+		end loop;
+
+		wait;
+	end process;
+
+	result(1) <= '1' when eq  else '0';
+	result(2) <= '1' when neq else '0';
+	result(3) <= '1' when lt  else '0';
+	result(4) <= '1' when lte else '0';
+	result(5) <= '1' when gt  else '0';
+	result(6) <= '1' when gte else '0';
+
+	test_inst: entity work.test
+		port map (
+			x => x,
+			y => y,
+
+			eq  => eq,
+			neq => neq,
+			lt  => lt,
+			lte => lte,
+			gt  => gt,
+			gte => gte
+		);
+end architecture;
diff --git a/testsuite/synth/enum01/test.vhdl b/testsuite/synth/enum01/test.vhdl
new file mode 100644
index 000000000..6709ea1c7
--- /dev/null
+++ b/testsuite/synth/enum01/test.vhdl
@@ -0,0 +1,25 @@
+use work.test_pkg.all;
+
+entity test is
+	port (
+		x : in number_t;
+		y : in number_t;
+
+		eq  : out boolean;
+		neq : out boolean;
+		lt  : out boolean;
+		lte : out boolean;
+		gt  : out boolean;
+		gte : out boolean
+	);
+end entity;
+
+architecture a of test is
+begin
+	eq  <= x  = y;
+	neq <= x /= y;
+	lt  <= x  < y;
+	lte <= x <= y;
+	gt  <= x  > y;
+	gte <= x >= y;
+end architecture;
diff --git a/testsuite/synth/enum01/test_pkg.vhdl b/testsuite/synth/enum01/test_pkg.vhdl
new file mode 100644
index 000000000..08fae8cee
--- /dev/null
+++ b/testsuite/synth/enum01/test_pkg.vhdl
@@ -0,0 +1,3 @@
+package test_pkg is
+	type number_t is (ONE, TWO, THREE);
+end package;
diff --git a/testsuite/synth/enum01/testsuite.sh b/testsuite/synth/enum01/testsuite.sh
new file mode 100755
index 000000000..511dcb1f4
--- /dev/null
+++ b/testsuite/synth/enum01/testsuite.sh
@@ -0,0 +1,14 @@
+#!/bin/sh
+
+. ../../testenv.sh
+
+analyze test_pkg.vhdl test.vhdl tb_test.vhdl
+elab_simulate tb_test --assert-level=error
+clean
+
+synth test_pkg.vhdl test.vhdl -e test > syn_test.vhdl
+analyze test_pkg.vhdl syn_test.vhdl tb_test.vhdl
+elab_simulate tb_test --ieee-asserts=disable-at-0 --assert-level=error
+clean
+
+echo "Test successful"