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authorTristan Gingold <tgingold@free.fr>2019-10-20 20:29:22 +0200
committerTristan Gingold <tgingold@free.fr>2019-10-20 20:29:22 +0200
commit91e21c17d6dd9ad4dd30439d6b95d8a03c0d3666 (patch)
treecd8a0e9467ef004424d34e2af5a783d1621aa3d1
parent56d1edff7fc40f745a47f6860bc2f9860d80052b (diff)
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netlists-disp_vhdl: display memory initialization value.
-rw-r--r--src/synth/netlists-disp_vhdl.adb48
1 files changed, 46 insertions, 2 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb
index d6e0d780f..1215d10e6 100644
--- a/src/synth/netlists-disp_vhdl.adb
+++ b/src/synth/netlists-disp_vhdl.adb
@@ -387,6 +387,48 @@ package body Netlists.Disp_Vhdl is
end case;
end Disp_Constant_Inline;
+ procedure Disp_Const_Bit (Cst : Net; Off : Uns32)
+ is
+ Inst : constant Instance := Get_Net_Parent (Cst);
+ Val : Uns32;
+ Zx : Uns32;
+ begin
+ case Get_Id (Inst) is
+ when Id_Const_Bit =>
+ Zx := 0;
+ Val := Get_Param_Uns32 (Inst, Param_Idx (Off / 32));
+ Val := Shift_Right (Val, Natural (Off mod 32)) and 1;
+ when others =>
+ raise Internal_Error;
+ end case;
+ Put (Bchar (Zx * 2 + Val));
+ end Disp_Const_Bit;
+
+ procedure Disp_Memory_Init (Val : Net; W : Width; Depth : Width)
+ is
+ Q : constant Character := Get_Lit_Quote (W);
+ begin
+ for I in 0 .. Depth - 1 loop
+ if I = 0 then
+ Put (" (");
+ else
+ Put (" ");
+ end if;
+ Put_Uns32 (I);
+ Put (" => ");
+ Put (Q);
+ for J in reverse 0 .. W - 1 loop
+ Disp_Const_Bit (Val, I * W + J);
+ end loop;
+ Put (Q);
+ if I /= Depth - 1 then
+ Put_Line (",");
+ else
+ Put_Line (");");
+ end if;
+ end loop;
+ end Disp_Memory_Init;
+
function Need_Name (Inst : Instance) return Boolean
is
Id : constant Module_Id := Get_Id (Inst);
@@ -616,9 +658,11 @@ package body Netlists.Disp_Vhdl is
Mem, (0 => Data_W - 1));
Disp_Template (" variable \o0 : \o0_type", Mem);
if Get_Id (Mem) = Id_Memory_Init then
- Disp_Template (" := \i0", Mem);
+ Put_Line (" :=");
+ Disp_Memory_Init (Get_Input_Net (Mem, 0), Data_W, Depth);
+ else
+ Put_Line (";");
end if;
- Put_Line (";");
Put_Line (" begin");
Port := Ports;