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| author | Tristan Gingold <tgingold@free.fr> | 2019-09-30 20:26:48 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-09-30 20:26:48 +0200 |
| commit | 91676ae056f62d2da2bd78ac5a3b6ba72447b738 (patch) | |
| tree | d7984fde952c653598d8a607d130efa2669a2188 | |
| parent | e21628dbda8dedd26f73d1685b547824c518c0ad (diff) | |
| download | ghdl-91676ae056f62d2da2bd78ac5a3b6ba72447b738.tar.gz ghdl-91676ae056f62d2da2bd78ac5a3b6ba72447b738.tar.bz2 ghdl-91676ae056f62d2da2bd78ac5a3b6ba72447b738.zip | |
synth-inference: handl 'EXPR and CLK' condition. Fix #951
| -rw-r--r-- | src/synth/synth-inference.adb | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/src/synth/synth-inference.adb b/src/synth/synth-inference.adb index e9a6eeab0..58c9ac142 100644 --- a/src/synth/synth-inference.adb +++ b/src/synth/synth-inference.adb @@ -161,8 +161,8 @@ package body Synth.Inference is Clk := Get_Input_Net (Inst, 0); when Id_And => -- Assume the condition is canonicalized, ie of the form: - -- CLK and EXPR. - -- FIXME: do it! + -- CLK and EXPR + -- EXPR and CLK declare I0 : constant Net := Get_Input_Net (Inst, 0); Inst0 : constant Instance := Get_Net_Parent (I0); @@ -174,6 +174,21 @@ package body Synth.Inference is -- output may be used by other nets. Clk := Get_Input_Net (Inst0, 0); Enable := Get_Input_Net (Inst, 1); + return; + end if; + end; + declare + I1 : constant Net := Get_Input_Net (Inst, 1); + Inst1 : constant Instance := Get_Net_Parent (I1); + begin + if Get_Id (Inst1) = Id_Edge then + -- INST is clearly not synthesizable (boolean operation on + -- an edge). Will be removed at the end by + -- remove_unused_instances. Do not remove it now as its + -- output may be used by other nets. + Clk := Get_Input_Net (Inst1, 0); + Enable := Get_Input_Net (Inst, 0); + return; end if; end; when others => |