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| author | Tristan Gingold <tgingold@free.fr> | 2022-08-09 21:44:27 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-08-10 03:00:10 +0200 |
| commit | 9034e7fba36540f0f38d9aa55e91391c5804d649 (patch) | |
| tree | 07114ae96e9edc4dbf95b24052c356fce6b817e9 | |
| parent | 62a87242d302568ce511a0e15b314e221cae391f (diff) | |
| download | ghdl-9034e7fba36540f0f38d9aa55e91391c5804d649.tar.gz ghdl-9034e7fba36540f0f38d9aa55e91391c5804d649.tar.bz2 ghdl-9034e7fba36540f0f38d9aa55e91391c5804d649.zip | |
synth-vhdl_oper.adb: fix mul uns uns. Fix #2169
| -rw-r--r-- | src/synth/synth-vhdl_oper.adb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb index 9cc3f5e95..920729c44 100644 --- a/src/synth/synth-vhdl_oper.adb +++ b/src/synth/synth-vhdl_oper.adb @@ -1233,7 +1233,7 @@ package body Synth.Vhdl_Oper is | Iir_Predefined_Ieee_Std_Logic_Unsigned_Mul_Slv_Slv => -- "*" (unsigned, unsigned) return Synth_Dyadic_Xxx_Xxx - (Ctxt, Id_Smul, Left.Typ.W + Right.Typ.W, + (Ctxt, Id_Umul, Left.Typ.W + Right.Typ.W, Left, Right, False, False, Expr); when Iir_Predefined_Ieee_Numeric_Std_Mul_Uns_Nat => -- "*" (unsigned, natural) |