testsuite/synth: add a test for #1162

2 files changed, 39 insertions, 0 deletions

diff --git a/testsuite/synth/issue1162/counter.vhdl b/testsuite/synth/issue1162/counter.vhdl
new file mode 100644
index 000000000..c698a74c7
--- /dev/null
+++ b/testsuite/synth/issue1162/counter.vhdl
@@ -0,0 +1,30 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity counter is
+	generic(
+		LEN    : positive := 1
+	);
+	port(
+		clk           : in std_ulogic;
+		reset_n       : in std_ulogic
+	);
+end counter;
+
+architecture behav of counter is
+	signal c : integer range 0 to LEN-1;
+begin
+	process(clk, reset_n)
+	begin
+		if reset_n = '0' then
+			c  <= 0;
+		elsif rising_edge(clk) then
+			if c = LEN-1 then
+				c <= 0;
+			else
+				c <= c + 1;
+			end if;
+		end if;
+	end process;
+end architecture;
diff --git a/testsuite/synth/issue1162/testsuite.sh b/testsuite/synth/issue1162/testsuite.sh
new file mode 100755
index 000000000..5474bc53c
--- /dev/null
+++ b/testsuite/synth/issue1162/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_analyze counter
+
+clean
+
+echo "Test successful"