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author | Tristan Gingold <tgingold@free.fr> | 2018-11-27 18:26:39 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2018-11-27 18:26:39 +0100 |
commit | 8d37b8b9a068d60f61b1c3296c945afe5f252309 (patch) | |
tree | cb0a14d2d0c847877f8c3112291ca7d4552480e4 | |
parent | b2325d1646d7166208060f858ec9f7b0a30e6249 (diff) | |
download | ghdl-8d37b8b9a068d60f61b1c3296c945afe5f252309.tar.gz ghdl-8d37b8b9a068d60f61b1c3296c945afe5f252309.tar.bz2 ghdl-8d37b8b9a068d60f61b1c3296c945afe5f252309.zip |
Reload registers for conditional binary operations.
Fix #708
-rw-r--r-- | src/ortho/mcode/ortho_code-x86-insns.adb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/ortho/mcode/ortho_code-x86-insns.adb b/src/ortho/mcode/ortho_code-x86-insns.adb index 5429df016..013a201e7 100644 --- a/src/ortho/mcode/ortho_code-x86-insns.adb +++ b/src/ortho/mcode/ortho_code-x86-insns.adb @@ -1901,6 +1901,8 @@ package body Ortho_Code.X86.Insns is when R_Any_Cc => Right := Gen_Insn (Right, R_Irm, Num); Left := Gen_Insn (Left, R_Any8, Num); + Left := Reload (Left, R_Irm, Num); + Right := Reload (Right, R_Any8, Num); Reg_Res := R_Ne; Alloc_Cc (Stmt, Num); Free_Insn_Regs (Left); |